A 2 GS/s, 6-bit DAC for UWB Applications In 0.18 ㎛ CMOS Technology

다국어 초록 (Multilingual Abstract)

To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 ㎜ CMOS technology and the area is 975 ㎛´ 775 ㎛. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 ㎓, the DAC can achieve a SFDR of 51 ㏈ for input signal of 6㎒, and a SFDR of 32.4 ㏈ for Nyquist input while the power consumption is 79 ㎽.

목차 (Table of Contents)

• Abstract
• Ⅰ. INTRODUCTION
• Ⅱ. DAC STRUCTURE AND KEY BUILDING BLOCKS
• Ⅲ. MEASUREMENT RESULTS
• Ⅳ. CONCLUSIONS
• REFERENCES