- Abstract
- Ⅰ. INTRODUCTION
- Ⅱ. PHASE INTERPOLATION SCHEMES
- Ⅲ. CLOCK FEEDBACK STRUCTURE
- Ⅳ. THE ARCHITECTURE OF THE PLL

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https://www.riss.kr/link?id=A100862598
2003
English
SCIE,SCOPUS,KCI등재
학술저널
181-187(7쪽)
0
상세조회0
다운로드목차 (Table of Contents)
Design and Implementation of Content Switching Network Processor and Scalable Switch Fabric
An Adaptive Spatial Depth Filter for 3D Rendering IP
A novel 622Mbps burst mode CDR circuit using two-loop switching
A design of 16-bit adiabatic Microprocessor core