실시간 successive-FFT 방식의 WDRC에 의한 완전 이식형 저전력 초소형 인공중이 전용 프로세서 설계 = A low power and subminiature processor for fully implantable middle ear hearing device using successive-FFT based wide dynamic range compression

다국어 초록 (Multilingual Abstract)

Recently, the population of hearing impaired people is increasing continuously and many people suffer from their hearing problems. To dealing with this problem, the various type hearing aid are being rapidly developed. Especially, the fully-implantable middle ear hearing device (F-IMEHD) is actively studied for sensorineural hearing loss people. The basic F-IMEHD system consists of implantable microphone, signal processor, and vibration transducer. The signal processor design must consider the input and output characteristics such as microphone output level and resonance of vibration transducer. In addition, signal processor had to accomplish the small size and low power consumption for implantation.
In this paper, we designed and implemented the small size and low power consumption signal processing chip for the F-IMEHD system. The designed chip consists of analog to digital converter (ADC), multi-channel wide dynamic range compression (WDRC), wireless communication, and output stage. In order to achieve the small size and low power consumption, we adopt the successive approximation register (SAR) ADC. The designed SAR ADC has 16 bit data resolution and operates on the 32 kHz sample rate. To verify the designed SAR ADC, the computer simulations and analog layout with the consideration of application specific integrated circuit (ASIC) have been performed. For the simulation, the Spectre (Cadence, USA) is used in a 0.18 ㎛ CMOS process library. Also, analog layout is designed by Virtuoso (Cadence, USA) and the dimension of designed SAR ADC are the width of 133.9 ㎛ and the length of 98.3 ㎛.
The multi-channel WDRC is designed as 4-channel system to adapt the frequency resonance of transducer. The frequency channels are separated to use 64 point FFT method. To reduce the amount of computation and memory utilization, FFT algorithm for frequency analysis is implemented without using the phased information of twiddle factor. The proposed WDRC algorithm based on the successive-FFT is not performs inverse FFT which have summation and multiplication for signal reconstruction. The proposed successive-FFT used repetition of the twiddle factor and it calculates only data summation for signal reconstruction. This method can be improved the speed of arithmetic operation and it has a advantage of low power consumption and small size design. The output of WDRC is converted to PDM (pulse density modulation) signal using the linear interpolation of 64 ㎑ over sample. The PDM output is not required additional DAC circuit because digital PDM is converted to analog signal through the vibration transducer which has low pass filter characteristics. And the output stage for the minimize the propagation delays is used tapered buffer strategy which consist of inverters.
To verify the proposed WDRC based on the successive-FFT and PDM output, the computer simulations and experiments have been performed. For the simulation, the Matlab (Mathworks Inc., USA) is used for frequency analysis, channel gain control and signal reconstruction. Also, an FPGA development board for the verification of performance is designed by ISE 14.7 (Xilinx, USA) and Modelsim-PE 10.3 (Mentor Graphics, USA) is used for simulation of verilog-HDL algorithm.
The communication data for wireless fitting is composed of 1 packet to 6 byte. The wireless communication algorithm is designed by ISE 14.7 and two modules which are TMS37157 (Texas instrument, USA) and nRF24L01 (Nordic semiconductor, Norway) can be selected for fitting. Through the in vitro fitting device, the fitting parameter is transmitted to F-IMEHD system and ACK (acknowledge character) that is same data is retransmitted to fitting device. And the total volume regardless of the channel can be controlled to 5 stage.
To verify the performance of the proposed processor, the computer simulation is implemented. According to the simulation results, the designed SAR ADC can be sampled input signal and it converted to 16 bit digital data with only 1 bit error rate. And successive-FFT based WDRD can be divided into 4 channel, controlled channel gain and reconstructed input signal under the Matlab environment and FPGA development board. Also, the proposed processor had 0.13 ㎽ power consumption at 1.8 V using the Cadence simulator.
Through the computer simulation and experimental results, it is verified that the proposed processor successfully worked with input signal sample, digital data conversion, channel division and reconstruction of input signal. Therefore, it is expected that the proposed processor can be applied for implementation of ASIC chip and improved the performance of F-IMEHD system.

목차 (Table of Contents)

• Ⅰ. 서 론
• Ⅱ. 완전 이식형 인공중이 장치
• 2.1 전용 프로세서의 필요성
• 2.1.1 완전 이식형 인공중이 장치의 구조
• 2.1.2 기존 완전 이식형 인공중이 장치 및 프로세서
• 2.1.3 범용 공기 전도형 보청기 프로세서
• 2.1.4 전용 프로세서 설계의 필요성
• Ⅲ. 제안한 전용 프로세서
• 3.1 제안한 프로세서의 구조
• 3.2 연속근사 SAR ADC의 설계
• 3.3 다채널 WDRC의 설계
• 3.3.1 WDRC의 개요 및 채널수의 선택
• 3.3.2 Successive-FFT 방식의 4채널 WDRC 설계
• 3.4 무선 피팅의 설계
• 3.5 출력단의 설계
• Ⅳ. 실험 및 고찰
• 4.1 컴퓨터 모의실험 결과
• 4.1.1 SAR ADC의 모의실험 결과
• 4.1.2 WDRC 알고리즘의 모의실험 결과
• Ⅴ. 결 론
• 참 고 문 헌
• 영 문 초 록