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      KCI등재 SCIE SCOPUS

      Threshold Voltage Control through Layer Doping of Double Gate MOSFETs

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      https://www.riss.kr/link?id=A82414132

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      다국어 초록 (Multilingual Abstract)

      Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an o therwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on...

      Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an o therwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

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      목차 (Table of Contents)

      • Abstract
      • Ⅰ. INTRODUCTION
      • Ⅱ. DEVICE STRUCTURE AND SIMULATION SCHEME OF LAYER-DOPED DG MOSFET
      • Ⅲ. EFFECT OF LAYER DOPING THE DG MOSFET CHANNEL
      • Ⅳ. CONCLUSIONS
      • Abstract
      • Ⅰ. INTRODUCTION
      • Ⅱ. DEVICE STRUCTURE AND SIMULATION SCHEME OF LAYER-DOPED DG MOSFET
      • Ⅲ. EFFECT OF LAYER DOPING THE DG MOSFET CHANNEL
      • Ⅳ. CONCLUSIONS
      • REFERENCES
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      참고문헌 (Reference)

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      2 D. Munteanu, "Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices" 47 (47): 1219-1225, 2003

      3 X. P. Wang, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs" 27 (27): 31-33, 2006

      4 J. Kavalieros, "Tri-Gate transistor architecture with High κ gate dielectrics, Metal gates and Strain engineering" 50-51, 2006

      5 A. Rahman, "Theory of ballistic nanotransistors" 50 (50): 1853-1864, 2003

      6 R.W.Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds" 8 (8): 251-259, 1975

      7 W. Y. Choi, "Stable threshold voltage extraction using Tikhonov’s regularization theory" 51 (51): 1833-1839, 2004

      8 G. Roy, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs" 53 (53): 3063-3070, 2006

      9 A. Asenov, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs" 50 (50): 1837-1850, 2003

      10 R. Venugopal, "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches" 92 (92): 3730-3739, 2002

      1 S. Svizhenko, "Two-dimensional quantum mechanical modeling of nanotransistors" 91 : 2343-2354, 2002

      2 D. Munteanu, "Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices" 47 (47): 1219-1225, 2003

      3 X. P. Wang, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs" 27 (27): 31-33, 2006

      4 J. Kavalieros, "Tri-Gate transistor architecture with High κ gate dielectrics, Metal gates and Strain engineering" 50-51, 2006

      5 A. Rahman, "Theory of ballistic nanotransistors" 50 (50): 1853-1864, 2003

      6 R.W.Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds" 8 (8): 251-259, 1975

      7 W. Y. Choi, "Stable threshold voltage extraction using Tikhonov’s regularization theory" 51 (51): 1833-1839, 2004

      8 G. Roy, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs" 53 (53): 3063-3070, 2006

      9 A. Asenov, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs" 50 (50): 1837-1850, 2003

      10 R. Venugopal, "Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches" 92 (92): 3730-3739, 2002

      11 K. Suzuki, "Scaling theory for Double-Gate SOI MOSFETs" 40 (40): 2326-2329, 1993

      12 A.Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: a statistical 3D ‘atomistic’ simulation study" 10 : 153-158, 1999

      13 A.Asenov, "Random dopant induced threshold voltage lowering and fluctuations in Sub-0.1μm MOSFETs: A 3-D atomistic simulation study" 45 : 2505-2513, 1998

      14 H. Zhong, "Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices" 467-470, 2001

      15 A. Asenov, "Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide" 47 : 805-812, 2000

      16 S.Datta, "Nanoscale device modeling: the Greens function method" 28 (28): 253-278, 2000

      17 G. Curatola, "Modelling and simulation challenges for nanoscale MOSFETs in the ballistic limit" 48 (48): 581-587, 2006

      18 A. Asenov, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness" 50 (50): 1254-1260, 2003

      19 A. R. Brown, "Intrinsic fluctuations in sub 10-nm Double-Gate MOSFETs introduced by discreteness of charge and matter" 1 (1): 195-200, 2002

      20 M. Ieong, "High performance double-gate device technology challenges and opportunities" 492-495, 2002

      21 H. Tanno, "Heavy B atomiclayer doping characteristics in Si epitaxial growth on B adsorbed Si(100) by ultraclean low-pressure CVD system" 53 (53): 877-879, 2009

      22 C. Y. Lin, "Fully silicided NiSi gate on La2O3 MOSFETs" 24 (24): 348-350, 2003

      23 D. S. Yu, "Fully Silicided NiSi and Germanided NiGe dual gates on SiO2 n- and p-MOSFETs" 24 (24): 739-741, 2003

      24 V. Misra, "Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS" 23 (23): 354-356, 2002

      25 F. Liu, "Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to stronginversion regions" 24 (24): 085005-, 2009

      26 R.W.Keyes, "Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics" 10 (10): 245-247, 1975

      27 H. Lu, "Effect of body doping on double-gate MOSFET characteristics" 23 (23): 2008

      28 J. Liu, "Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers" 26 (26): 228-230, 2005

      29 D. J. Frank, "Devicescaling limits of Si MOSFETs and their application dependencies" 89 : 259-288, 2001

      30 T.-L.Li,C.-H.Hu,W.-L.Ho,H.C.H.Wang,and C.-Y.Chang, "Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys" 52 (52): 1172-1179, 2005

      31 C.-H. Lu, "Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO2 and HfO2" 26 (26): 445-447, 2005

      32 J. K. Schaeffer, "Challenges for the integration of metal gate electrodes" 287-290, 2004

      33 K.Natori, "Ballistic Metal-Oxide-Semiconductor Field Effect Transistor" 76 (76): 4879-4890, 1994

      34 J. Murota, "Atomically controlled processing for Group IV semiconductors by chemical vapor deposition" 45 (45): 6767-6785, 2006

      35 B. Tillack, "Atomic layer processing for doping of SiGe" 508 (508): 279-283, 2006

      36 Y.Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric doublegate MOSFETs" 48 (48): 2861-2869, 2001

      37 R. Lin, "An djustable work function technology using Mo gate for CMOS devices" 23 (23): 49-51, 2002

      38 X.Zhou, "A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling" 46 (46): 807-809, 1999

      39 Y. Taur, "25 nm CMOS design considerations" 789-792, 1998

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      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
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      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
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