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      3차원 패키징용 TSV의 열응력에 대한 열적 전기적 특성 = A study on Electrical Characteristic and Thermal Shock Property of TSV for 3-Dimensional Packaging

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      https://www.riss.kr/link?id=A103463865

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      다국어 초록 (Multilingual Abstract)

      Less power consumption, lower cost, smaller size and more functionality are the increasing demands forconsumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet thisrequirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usuallybeen chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayerinterconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. Thisstudy discribe the thermal stress reliability trend for successful implementation of 3-D packaging.
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      Less power consumption, lower cost, smaller size and more functionality are the increasing demands forconsumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet thisrequirement because it can sup...

      Less power consumption, lower cost, smaller size and more functionality are the increasing demands forconsumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet thisrequirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usuallybeen chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayerinterconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. Thisstudy discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

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      참고문헌 (Reference)

      1 A. J. Joseph, "Through- Silicon Vias Enable Next-Generation SiGe Power Amplifiers for Wireless Communications" 52 (52): 635-, 2008

      2 B. Wunderle, "Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon" MRS 67-, 2007

      3 K. H. Lu, "Thermo-Mechanical Reliability of 3-D ICs Containing Through Silicon Vias" CPMT 630-, 2009

      4 K. H. Lu, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects" IEEE (CPMT) 40-, 2010

      5 K. Lu, "Temperature Dependent Thermal Stress Determination for Through-Silicon-Vias (TSV) by Combining Bending Beam Technique with Finite Element Analysis" IEEE Components, Packaging and Manufacturing Technology Society (CPMT) 1475-, 2011

      6 H. J. Chung, "TSV Technology and Its Application to DRAM" IEEE Solid-State Circuits Society 130-, 2010

      7 M. Amagai, "TSV Stress Testing and Modeling" IEEE (CPMT) 1273-, 2010

      8 D. S. Tezcan, "Sloped Through Wafer Vias for 3D Wafer Level Packaging" IEEE (CPMT) 643-, 2007

      9 "Samsung TSV 2013 Diagram 3D Package"

      10 T. Frank, "Resistance Increase due to Electromigration Induced Depletion under TSV" IEEE 341-, 2011

      1 A. J. Joseph, "Through- Silicon Vias Enable Next-Generation SiGe Power Amplifiers for Wireless Communications" 52 (52): 635-, 2008

      2 B. Wunderle, "Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon" MRS 67-, 2007

      3 K. H. Lu, "Thermo-Mechanical Reliability of 3-D ICs Containing Through Silicon Vias" CPMT 630-, 2009

      4 K. H. Lu, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects" IEEE (CPMT) 40-, 2010

      5 K. Lu, "Temperature Dependent Thermal Stress Determination for Through-Silicon-Vias (TSV) by Combining Bending Beam Technique with Finite Element Analysis" IEEE Components, Packaging and Manufacturing Technology Society (CPMT) 1475-, 2011

      6 H. J. Chung, "TSV Technology and Its Application to DRAM" IEEE Solid-State Circuits Society 130-, 2010

      7 M. Amagai, "TSV Stress Testing and Modeling" IEEE (CPMT) 1273-, 2010

      8 D. S. Tezcan, "Sloped Through Wafer Vias for 3D Wafer Level Packaging" IEEE (CPMT) 643-, 2007

      9 "Samsung TSV 2013 Diagram 3D Package"

      10 T. Frank, "Resistance Increase due to Electromigration Induced Depletion under TSV" IEEE 341-, 2011

      11 Hyoung-Seuk Choi, "Prediction of Reliability on Thermoelectric Module through Accelerated Life Test and Physics-of-Failure" 대한금속·재료학회 7 (7): 271-275, 2011

      12 J. Knickerbocker, "Overview of Candidate Device Technologies for Storage Technology" 52 (52): 449-, 2008

      13 P. Dixit, "Numerical and Experimental Investigation of Thermomechanical Deformation in High Aspect-Ratio Electroplated Through-Silicon Vias" 155 (155): H981-, 2008

      14 "Nokia 2013 Packaging Roadmap"

      15 Z. Chen, "Modeling of Electromigration of the Through Silicon Via Interconnects" IEEE 1221-, 2010

      16 J. Pak, "Modeling of Electromigration in Through-Slicon-Via Based 3D IC" IEEE (CPMT) 1420-, 2011

      17 R. R. Tummala, "Microelectronics Packaging Handbook, 2nd Ed." Chapman & Hall 1997

      18 A. Budiman, "Measurement of Stresses in Cu and Si around Through-Silicon Via by Synchrotron X-Ray Micro Diffraction for 3- Dimensional Integrated Circuits" 52 (52): 530-, 2012

      19 T. Jiang, "Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-Silicon-Vias" 53 (53): 53-, 2013

      20 Z. Zhang, "Investigate the Microstructure Changes in Cu Through-Silicon Vias(TSVs) under Thermal Process" IEEE (CPMT) 1273-, 2012

      21 M. Jung, "Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC" IEEE/ ACM 563-, 2011

      22 X. Liu, "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)" IEEE (CPMT) 624-, 2009

      23 S. -H. Seo, "Failure Mechanism of Copper Through- Silicon Vias under Biased Thermal Stress" 546 : 14-, 2013

      24 X. Liu, "Failure Analysis of Through-Silicon Vias in Free- Standing Wafer under Thermal-Shock Test" 53 (53): 70-, 2013

      25 Y. C. Tan, "Electromigration Performance of Through Silicon Via (TSV)-a Modeling Approach" 50 (50): 1336-, 2010

      26 정일호, "Electrical Characteristics and Thermal Shock Properties of Cu-Filled TSV Prepared by Laser Drilling" 대한금속·재료학회 9 (9): 389-392, 2013

      27 I. H. Jeong, "Electrical Characteristic and Thermal Shock Property of Cu Filled Through Silicon Via for 3-Dimensional Packaging" University of Seoul 2013

      28 Santosh Kumar, "Analysis of high speed shear characteristics of Sn-Ag-Cu solder joints" 대한금속·재료학회 7 (7): 365-373, 2011

      29 "3-D TSV Interconnects, in Equipment & Materials 2008 Report" Yole Development 158-, 2008

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2022 평가예정 계속평가 신청대상 (계속평가)
      2021-12-01 평가 등재후보로 하락 (재인증) KCI등재후보
      2018-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2015-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2011-06-28 학술지명변경 한글명 : 마이크전자 및 패키징학회지 -> 마이크로전자 및 패키징학회지
      외국어명 : The Microelectronics and Packaging Society -> Jornal of the Microelectronics and Packaging Society
      KCI등재
      2011-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2009-01-01 평가 등재 1차 FAIL (등재유지) KCI등재
      2007-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2004-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2003-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2001-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.48 0.48 0.43
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.39 0.35 0.299 0.35
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