설계 초기 단계에서 전력/클록 네트워크를 고려한 라우팅 밀집도 예측 방법론 = Power/Clock Network-Aware Routing Congestion Estimation Methodology at Early Design Stage

다국어 초록 (Multilingual Abstract)

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

참고문헌 (Reference)

1 Jurjen Westra, "Towards Integration of Quadratic Placement and Pin Assignment" 2005

2 Bella Dubrov, "Pin Assignment Using Stochastic Local Search Constraint Programming" (5732) : 35-49, 2009

3 Tianpei Zhang, "Optimized Pin Assignment for Lower Routing Congestion After Floorplanning Phase" 6-7, 2002

4 A. P. Chandrakasan, "Low Power Digital CMOS Design" Kluwer 1995

5 Jeffery A. Davis, "Interconnect Technology and Design for Gigascale Integration" Kluwer Academic Publishers 2003

6 M. Wang, "Congestion minimization during placement" 19 : 1140-1148, 2000

7 Chiu-Wing Sham, "Congestion Prediction in Early Stages of Physical Design" 14 (14): 2009

8 Xiaojian Yang, "Congestion Estimation During Top-Down Placement" 2001

9 J. Cong, "Bounded-Skew Clock and Steiner Routing" 4 (4): 1999

10 J. A. Davis, "A stochastic wire-length distribution for gigascale integration(GSI)—Part I:Derivation and validation" 45 : 580-589, 1998