1 J. Jang, "Vertical cell array using TCAT technology for ultra-high density NAND flash memory" 192-193, 2009
2 P. C. Y. Chen, "Threshold-alterable Si-gate MOS devices" 24 (24): 584-586, 1977
3 H. A. R. Wegner, "The variable threshold transistor, a new electricallyalterable, non-destructive read-only storage device" 13 : 70-, 1967
4 J.-P. Colinge, "Silicon-on-Insulator Technology: Materials to VLSI" Kluwer Academic Publishers 1997
5 M. White, "On the Go with SONOS" 16 (16): 22-31, 2000
6 C. H. Lee, "Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure" 118-119, 2008
7 W. Kwon, "Compact NAND flash memory cell design utilizing backside charge storage" 2010
8 H. Tanaka, "Bit cost scalable technology with punch and plug process for ultra high density flash memory" 14-15, 2007
9 H. Silva, "A nanoscale memory and transistor using backside trapping" 3 (3): 264-269, 2004
10 "2012 iSuppli annual report" 2012
1 J. Jang, "Vertical cell array using TCAT technology for ultra-high density NAND flash memory" 192-193, 2009
2 P. C. Y. Chen, "Threshold-alterable Si-gate MOS devices" 24 (24): 584-586, 1977
3 H. A. R. Wegner, "The variable threshold transistor, a new electricallyalterable, non-destructive read-only storage device" 13 : 70-, 1967
4 J.-P. Colinge, "Silicon-on-Insulator Technology: Materials to VLSI" Kluwer Academic Publishers 1997
5 M. White, "On the Go with SONOS" 16 (16): 22-31, 2000
6 C. H. Lee, "Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure" 118-119, 2008
7 W. Kwon, "Compact NAND flash memory cell design utilizing backside charge storage" 2010
8 H. Tanaka, "Bit cost scalable technology with punch and plug process for ultra high density flash memory" 14-15, 2007
9 H. Silva, "A nanoscale memory and transistor using backside trapping" 3 (3): 264-269, 2004
10 "2012 iSuppli annual report" 2012