Switched-currents : an analogue technique for digital technology

목차 (Table of Contents)

• CONTENTS
• 1 Introduction / C. Toumazou ; J. B. Hughes ; N. C. Battersby = 1
• 1.1 VLSI Technology = 1
• 1.2 The Analogue Dilemma = 1
• 1.3 Switched-Currents = 3
• 1.4 An Analogue Technique For Digital Technology = 3
• 1.5 Book Style = 4
• 1.6 Conclusion = 7
• References = 8
• 2 The Evolution of Analogue Sampled-Data Signal Processing / N. C. Battersby ; C. Toumazou = 9
• 2.1 Introduction = 9
• 2.2 The Evolution of Analogue Sampled-Data Techniques = 9
• 2.2.1 Early work = 10
• 2.2.2 Bucket brigade devices = 10
• 2.2.3 Charge coupled devices = 11
• 2.2.4 Switched-capacitors = 13
• 2.3 The Role of Analogue Sampled-Data Signal Processing = 16
• 2.4 Processing Trends and their Irnpact on Analogue Circuits = 18
• 2.5 Current-Mode Analogue Signal Processing = 23
• 2.6 Summary = 25
• References = 25
• Basic Cells
• 3 Switched-Current Architectures and Algorithms / J. B. Hughes ; N. C. Bird ; I. C. Macbeth = 30
• 3.1 Introduction = 30
• 3.2 Switched-Capacitor Background = 30
• 3.2.1 Non-inverting integrator = 31
• 3.2.2 Inverting integrator = 32
• 3.2.3 Inverting amplifier = 32
• 3.2.4 Generalised integrator = 33
• 3.2.5 Subtracting integrator = 34
• 3.2.6 Switched-capacitor characteristics = 35
• 3.3 Switched-Current Systems = 35
• 3.4 Delay Modules = 37
• 3.4.1 Current memory cell = 37
• 3.4.2 Delay cell = 38
• 3.4.3 Delay line = 39
• 3.5 lntegrator Modules = 39
• 3.5.1 Non-inverting integrator = 39
• 3.5.2 Non-inverting damped integrator = 41
• 3.5.3 Sensitivity = 43
• 3.5.4 Inverting damped integrator = 44
• 3.5.5 Inverting damped amplifier = 45
• 3.5.6 Generalised integrator = 46
• 3.5.7 Bilinear z-transform integrator = 48
• 3.5.8 Comparison with the switched-capacitor integrator = 49
• 3.5.9 Integrator-based biquadratic section = 49
• 3.6 Differentiator Modules = 54
• 3.6.1 Inverting differentiator = 54
• 3.6.2 Generalised inverting differentiator = 55
• 3.6.3 Non-inverting differentiator = 57
• 3.6.4 Generalised non-inverting differentiator = 59
• 3.6.5 Bilinear z-transform differentiator = 61
• 3.6.6 Differentiator-based biquadratic section = 62
• 3.7 Filter Synthesis Example 6th Order Lowpass Filter = 64
• 3.8 Summary = 68
• References = 69
• 4 Switched-Current Limitations and Non-Ideal Behaviour / J. B. Hughes ; W. Redman-White = 71
• 4.1 Introduction = 71
• 4.2 Mismatch Errors = 71
• 4.2.1 Unity gain Current memory = 71
• 4.2.2 Non-unity gain current memory = 76
• 4.3 Output-Input Conductance Ratio Errors = 77
• 4.3.1 Memory cell response with conductance ratio errors = 78
• 4.3.2 Integrator response with conductance ratio errors = 81
• 4.3.3 Comparison with switched-capacitor integrator = 84
• 4.3.4 Simulations = 85
• 4.4 Settling Errors = 86
• 4.4.1 Underdamped response = 87
• 4.4.2 Critically damped response = 88
• 4.4.3 Overdamped response = 88
• 4.4.4 Memory cell response with settling errors = 90
• 4.4.5 Integrator response with settling errors = 93
• 4.4.6 Comparison with switched-capacitor integrator = 98
• 4.4.7 Simulations = 99
• 4.5 Charge Injection Errors = 99
• 4.5.1 Switched-capacitor charge injection = 100
• 4.5.2 Current memory charge injection = 103
• 4.5.3 Analysis of charge injection errors = 108
• 4.5.4 Memory Cell response with charge injection errors = 111
• 4.5.5 Integrator frequency response with charge injection errors = 113
• 4.6 Noise Errors = 117
• 4.6.1 Noise analysis of switched-current memory cells = 117
• 4,6.1.1 Simulations = 121
• 4.6.1.2 Correlated double sampling = 121
• 4.6.1.3 Dynamic range = 123
• 4.6.2 Integrator noise analysis = 125
• 4.6.2.1 Simulations = 129
• 4.6.2.2 Dynamic range = 130
• 4.7 SummaTy = 131
• References = 134
• 5 Noise in Switched-Current Circuits / S. J. Daubert = 136
• 5.1 Overview = 136
• 5.2 Transistor Noise = 137
• 5.3 Current Mirror Noise = 139
• 5.4 Current Copier Noise = 143
• 5.4.1 Relative importance of switch and transconductor noise in a current copier = 144
• 5.4.2 Transfer function approach = 147
• 5.5 ConcIusion = 154
• References = 154
• 6 Switched-Current Circuit Design Tecniques / J. B. Hughes ; K. W. Moulding ; D. M. Pattullo = 156
• 6.1 Introduction = 156
• 6.2 Feedback Techniques = 156
• 6.2.1 Op-amp active memory cell = 157
• 6.2.2 Grounded-gate active memory cell = 160
• 6.2.3 Simple cascode memory cell = 163
• 6.2.4 Folded-cascode memory cell = 167
• 6.2.5 Regulated cascode = 170
• 6.2.6 Regulated folded-cascode memory cell = 172
• 6.2.7 Integrators = 172
• 6.3.1 Basic fully-differential current memory cell = 174
• 6.3.2 Folded-cascode fully-differential current memory and integrator = 177
• 6.3.3 Single-ended to fully-differential equivalence = 179
• 6.3.4 Charge injection = 181
• 6.4 Summary = 188
• 7 Class AB Switched-Current Techniques / N. C. Battersby ; C. Toumazou = 191
• 7.1 Introduction = 191
• 7.2 Memory Cell = 192
• 7.3 Filter Building Blocks = 194
• 7.3.1 Delay cells = 194
• 7.3.2 Integrator circuits = 194
• 7.3.3 Differentiator circuits = 196
• 7.4 Performance Limitations = 197
• 7.5 Biquadratic Filter Example = 200
• 7.6 Conclusions = 202
• Acknowledgements = 202
• References = 202
• Filters
• 8 Switched-Current Filters / N. C. Battersby ; C. Toumazou = 204
• 8.1 Introduction = 204
• 8.2 Biquadratic Filter Sections = 204
• 8.2.1 Integrator based sections = 205
• 8.2.2 Example: integrated biquadratic filter = 207
• 8.2.3 Differentiator based sections = 212
• 8.3 Ladder Filters = 214
• 8.3.1 Example: integrated elliptic filter = 214
• 8.4 FIR Filters = 222
• 8.5 Wave Active Filters = 223
• 8.6 Transposition of Switched-Capacitor Filters = 223
• 8.7 Switched-Transconductance Filters = 223
• 8.7.1 Switched-transconductance concept = 224
• 8.7.2 Composite elements = 226
• 8.7.3 Filter applications = 227
• Acknowledgements = 230
• References = 230
• 9 A Svitched-Capacitor to Switched-Current Conversion Method / G. W. Roberts ; A. S. Sedra = 232
• 9.1 Introduction = 232
• 9.2 The Switched-Current Technique = 233
• 9.3 Comparing the SFGs of SI and SC Integrator Circuits = 235
• 9.4 SI Filter Circuits with Finite Transmission Zeros = 241
• 9.5 SI Filter Circuits using Bilinear Integrators = 245
• 9.6 Conclusions = 250
• Acknowledgement = 251
• References = 251
• 10 Switched-Current Video Signal Processing / J. B. Hughes ; K. W. Moulding = 252
• 10.1 Introduction = 252
• 10.2 Basic Signal Processing Cells = 253
• 10.2.1 Delay line = 253
• 10.2.2 Integrator and differentiator cells = 255
• 10.2.3 FIR cells = 255
• 10.3 Practical SI Signal Processing Cells = 256
• 10.3.1 Active negative feedback = 256
• 10.3.2 Fully differential circuits = 259
• 10.4 Mermory Cell Design = 261
• 10.4.1 Transmission error = 261
• 10.4.1.1 Conductance ratio error = 261
• 10.4.1.2 Charge injection errors = 262
• 10.4.2 Settling behaviour = 263
• 10.4.2.1 Linear settling = 263
• 10.4.2.2 Non-Iinear settling = 265
• 10.4.3 Signal-to-noise ratio = 265
• 10.5 Video 1C Test Circuit = 266
• 10.5.1 Output waveforms = 269
• 10.5.2 Amplitude responses = 269
• 10.5.4 Harmonic distortion = 271
• 10.5.5 Summary of performance = 272
• 10.6 Discussion and Conclusions = 272
• 10.7 References = 273
• Argendix 10A = 274
• Appendix 10B = 275
• Appendix 10C = 277
• 11 Switched-Current Wave Analogue Filters / A. Rueda ; A. Y$$\acute u$$fera ; J. L Huertas = 279
• 11.1 Introduction and Motivations = 279
• 11.2 Wave Filters = 281
• 11.2.1 General principles = 281
• 11.2.2 Wave filter synthesis procedure = 284
• 11.2.3 Scaling techniques = 287
• 11.3 Switched-Current Wave Filter Design = 287
• 11.3.1 Basic building blocks = 288
• 11.3.2 Limitations and non-idealities of the building blocks = 291
• 11.4 Programmable Band-pass Filter Structures = 295
• 11.4.1 Filter synthesis = 295
• 11.4.2 Programmable filter implementation = 296
• 11.5 Design Examples = 297
• 11.6 Conclusions = 302
• References = 302
• Data Converters
• 12 Algorithmic and Pipelined A/D Converters / D. Nairn = 304
• 12.1 Introduction = 304
• 12.2 Architectures For Switched-Current ADCs = 305
• 12.2.1 Algorithmic ADCs = 305
• 12.2.2 Pipelined ADCs = 307
• 12.2.3 Summary = 308
• 12.3 Building Blocks = 308
• 12.3.1 Current-samplers = 308
• 12.3.2 Current divide-by-two = 312
• 12.3.3 Current comparators = 313
• 12.3.4 Switches in switched-current circuits = 314
• 12.3.5 Summary = 316
• 12.4 Converter Implementation and Examples = 316
• 12.4.1 Algorithmic ADCs = 316
• 12.4.2 Pipelined ADCs = 319
• 12.5 Limitations = 319
• 12.5.1 Systematic errors = 319
• 12.5.2 Random errors = 320
• 12.6 Conclusions = 320
• References = 321
• 13 High Resolution Algorithmic A/D Converters based on Dynamic Current Memories / P. Deval =323
• 13.1 Introduction = 323
• 13.2 CMOS dynamic current memory = 323
• 13.3 Conversion algorithm with reduced dynamic range of the memorised currents = 325
• 13.4 Conversion error = 327
• 13.5 Design of dynamic current memories for use in cyclic ADCs = 328
• 13.5.1 Equivalent time constant of the memory = 328
• 13.5.2 Charge injection error = 330
• 13.5.3 Sampled noise = 334
• 13.5.4 Leakage currents = 335
• 13.5.5 Output conductance = 336
• 13.5.6 Current comparison = 340
• 13.5.7 Comparator offset compensation = 341
• 13.5.8 Clipping the comparator's input voltage = 342
• 13.5.9 Controlling the "on" conductance of the sampling switch = 343
• 13.5.10 Input multiplexer = 343
• 13.6 Technology scaling = 344
• 13.7 Pipelined converter = 344
• 13.8 Experimental results and measurements = 345
• 13.9 Summary = 347
• Acknowledgements = 347
• References = 348
• 14 Building Blocks for Switched-Current Sigma-Delta Converters / G. W. Roberts ; P. J. Crawley = 350
• 14.1 Introduction = 350
• 14.2 Sigma-Delta A/D Conversion = 350
• 14.3 The SI Circuit Technique = 354
• 14.4 Additional Current-Mode Circuits = 363
• 14.5 SI DISDM Design = 365
• 14.5.1 The current mirror design approach = 365
• 14.5.2 The component-invariant design approach = 376
• 14.6 Conclusions = 379
• Acknowledgements = 379
• References = 380
• 15 Continuous Calibration D/A Conversion / W. Groeneveld ; H. Schouwenaars ; C. Bastiaansen ; H. Termeer = 381
• 15.1 Accuracy of Audio D/A Converters = 381
• 15.1.1 Introduction = 381
• 15.1.2 Linearity considerations = 381
• 15.1.3 Basic calibration principle = 382
• 15.1.4 Imperfections = 383
• 15.1.5 Numerical example = 385
• 15.1.6 Improved calibration technique = 386
• 15.1.7 Continuous current calibration = 388
• 15.2 16-bit Audio D/A Converter Architecture = 388
• 15.2.1 Block diagram = 388
• 15.2.2 Calibration circuitry and current cell = 389
• 15.2.3 Measurement results = 390
• 15.3 Calibrated Noise Shaping D/A Converter = 393
• 15.3.1 Introduction = 393
• 15.3.2 General design considerations = 394
• 15.3.3 Converter architecture considerations = 396
• 15.3.4 D/A converter block diagram = 397
• 15.3.5 Reference current adjustment = 398
• 15.3.6 Digital continuous calibration = 399
• 15.3.7 Bi-directional calibrating current cell = 399
• 15.3.8 Measurement results = 400
• 15.4 Conclusions = 402
• Acknowledgements = 402
• References = 403
• Other Applications
• 16 Dynamic Current Mirrors / G. Wegmann = 404
• 16.1 Introduction = 404
• 16.2 Current Copiers = 405
• 16.2.1 Principle of current copier and dynamic current mirrors = 405
• 16.2.2 Principal accuracy limitations = 406
• 16.2.3 Cascoded structure = 408
• 16.2.4 Current copier with reduced transconductance gmm△ = 409
• 16.2.5 Dynamic current mirror structures = 410
• 16.2.6 Multiple dynamic current mirrors (1:1) = 412
• 16.2.7 Dividing current mirror: principle of the division by 2($$I_out $$＝ $$I_in$$/2) = 414
• 16.3 Accuracy Limitations = 417
• 16.3.1 Influence of drain voltage variations = 417
• 16.3.1.1 Output conductance gds = 417
• 16.3.1.2 Capacitive divider $$C_gd$$ - C = 418
• 16.3.1.3 Direct charge flow path = 419
• 16.3.2 Leakage currents = 419
• 16.3.3 Charge injection by analogue switches = 421
• 16.3.3.1 Interfering parameters = 420
• 16.3.3.2 Strategies = 422
• 16.3.3.3 Reduction of the turn-on voltage of the sampling switch = 423
• 16.3.3.4 Two-phase feedback = 425
• 16.4 Noise Analysis = 426
• 16.4.1 Noise sources = 426
• 16.4.2 Analysis of direct noise sources = 427
• 16.4.3 Description of sampling and autozeroing effects = 428
• 16.4.4 Analysis of sampling and autozeroing transfer functions = 431
• 16.4.5 Calculation of sample-and-hold component △$$V_h$$(f) = 433
• 16.4.6 Calculation of the direct component △$$V_D$$(f) = 433
• 16.4.7 Autozero transfer function =433
• 16.4.8 Voltage noise spectral power density $$S_V$$(f) = 435
• 16.4.9 Analysis of aliasing effects using the equivalent noise bandwidth technique = 436
• 16.4.9.1 White noise in first and second-order low-pass filters = 436
• 16.4.9.2 White noise aliasing effect in a current copier = 437
• 16.4.9.3 1/f noise in first and second-order low-pass filter = 438
• 16.4.9.4 1/f aliasing effect in a current copier = 439
• 16.4.10 Noise spectral power density $$S_v$$(f) = 440
• 16.4.10.1 White noise due to main transistor Tm = 440
• 16.4.10.2 Noise spectral power density $$S_VT$$(f) in the baseband = 441
• 16.5 Dynamic Behaviour = 442
• 16.5.1 Critical switching configurations = 442
• 16.5.1.1 Influence of clock delay = 442
• 16.5.1.2 Influence on the output current - AC and DC = 444
• 16.5.2 Speed-accuracy trade-off = 445
• 16.5.2.1 Settling time constant = 445
• 16.5.2.2 Speed-accuracy trade-off = 445
• 16.6 Measurements = 446
• 16.6.1 AC measurements = 447
• 16.6.1.1 Variations of input voltage $$V_in$$(t) and output current $$I_out$$(t) = 447
• 16.6.2 DC measurements = 448
• 16.6.2.1 Multiplying mirror of ratio 1 = 448
• 16.6.2.2 Basic cell with a reduced transconductance $$g_mm$$△ = 450
• 16.6.2.3 Influence of the clock frequency = 451
• 16.6.3 Noise measurements = 452
• 16.7 Conclusion = 453
• References = 453
• Appendix 16A = 456
• Appendix 16B = 458
• 17 Switched-Current Cellular Neural Networks for Image Processing / A. Rodriguez-V$$\acute a$$zquez ; S. Espejo ; J. Huertas ; R. Dom$$\acute i$$nguez-Castro = 459
• 17.1 Introduction = 459
• 17.2 The DT-CNN Model = 461
• 17.2.1 Network architecture and dynamics = 461
• 17.2.2 Network processing and operating modes = 463
• 17.3 Basic Building Blocks for SI DTCNNs = 466
• 17.3.1 Cell operators = 466
• 17.3.2 Current-mode replication and scaling = 467
• 17.3.3 Cell non-linearity = 468
• 17.3.4 Delay block = 470
• 17.3.5 Current mode CNN conceptual cell schematics = 471
• 17.4 CMOS Current-Mode CNN Design Issues = 472
• 17.4.1 CMOS mirror circuits static non-idealities and sizing equations = 472
• 17.4.2 CMOS current mode dynamic operators non-idealities = 477
• 17.4.3 Programmability issues for current-mode blocks = 477
• 17.4.4 Bias current selection area, power and reliability = 479
• 17.5 lnput-Output Strategies = 480
• 17.6 Discussion and Perspectives = 482
• References = 483
• Analysis Simulation and Test
• 18 Test for Switched-Current Circuits / P. Wrighton ; G. Taylor ; I. Bell ; C. Toumazou = 487
• 18.1 Introduction = 487
• 18.2 Basic concepts for the test of SI cells = 488
• 18.2.1 Injection and simulation of faults in SI cells = 489
• 18.2.2 Fault detection and detectability measures = 490
• 18.3 Test vector analysis = 493
• 18.3.1 Effect of test stimulus period = 494
• 18.3.2 Different profile test stimuli = 496
• 18.3.2.1 Overall coverage = 496
• 18.3.2.2 Transistor level analysis = 497
• 18.3.2.3 Individual faults groups and failure modes = 499
• 18.4 Built In Self Test for SI cells = 501
• 18.4.1 Functional inversion test circuit = 502
• 18.4.1.1 Fault coverage = 505
• 18.5 Conclusions and future work = 506
• Acknowledgements = 507
• References = 507
• 19 Analysis of Switched-Current Filters / A. C. M. de Queiroz = 508
• 19.1 Introduction = 508
• 19.2 Frequency-Domain Nodal Analysis of Switched-Current Filters = 509
• 19.3 Refinements to the Basic Algorithm = 512
• 19.4 Voltage Sources in Nodal Analysis = 513
• 19.5 Interpolation of z-transforms = 514
• 19.6 Time-Domain Analysis = 517
• 19.7 Sensitivity Analysis = 518
• 19.8 Conclusions = 525
• References = 526
• 20 Non-linear Behaviour of Switched-Current Memory Circuits / G. W. Roberts ; P. J. Crawley = 528
• 20.1 Introduction = 528
• 20.2 Basic Memory Cell Operation = 529
• 20.3 Small-Signal Behaviour of the Memory Cell = 532
• 20.4 Large-Signal Behaviour of the Memory Cell = 536
• 20.4.1 A total harmonic distortion bound = 539
• 20.4.2 Comparing THD bound with simulation results = 543
• 20.4.3 Experimental confirmation of the THD bound = 545
• 20.5 Conclusions = 545
• Acknowledgement = 546
• References = 546
• Future Directions
• 21 GaAs MESFET Switched-Current Circuits / C. Toumazou ; N. C. Battersby = 548
• 21.1 Introduction = 548
• 21.2 Ga-As Versus Silicon Technology For Analogue Design = 548
• 21.3 MESFET Modelling = 550
• 21.4 GaAs MESFET Current-Mirror Techniques = 553
• 21.4.1 Cross-coupled MESFET pair = 553
• 21.4.2 Linear current-mirror = 554
• 21.4.3 Cascoding = 556
• 21.6 Towards GaAs MESFET Switched-Current Techniques = 559
• 21.6.1 Basic memory cell = 560
• 21.6.2 Linear non-inverting memory cell = 561
• 21.6.3 Fully differential, linear transconductance GaAs switched-current cell = 563
• 21.6.4 Generalised integrator = 564
• 21.6.5 Performance limitations = 565
• 21.7 Circuit techniques for enhanced performance = 567
• 21.7.1 Dummy switch compensation = 567
• 21.7.2 Cascoded memory cells = 568
• 21.8 Simulation results = 569
• 21.8.1 Fully cascoded memory cell = 570
• 21.8.2 Damped integrator = 572
• 21.8.3 Biquadratic filter example = 573
• 21.9 Discussion and Conclusion = 574
• Acknowledgements = 575
• References = 575
• 22 Switched-Currents: State-of-the-Art and Future Directions / C. Toumazou ; N. C. Battersby ; J. B. Hughes = 577
• 22.1 Introduction = 577
• 22.2 Switched-currents: an analogue technique for digital technology = 577
• 22.3 Future Research Directions = 584
• 22.4 Towards total memory cell error cancellation schemes = 584
• 22.4.1 Algorithmic memory cell = 585
• 22.4.2 $$S^2 $$I memory cell = 586
• 22.3.3 Noise performance = 588
• 22.3.4 Towards low power =. 588
• 22.3.5 Tuning schemes = 588
• 22.3.6 Filter building blocks = 589
• 22.3.7 Data converters = 589
• 22.3.8 GaAs technology = 589
• 22.3.9 CAD, simulation and test = 589
• 22.4 Conclusions = 590
• References = 590
• Index = 591