1 E. Mastrovito, "VLSI Architectures for Computation in Galois Fields" dept. of electrical eng. : 1991.
2 Chin-Liang Wang, "Systolic Array Implementation of Multipliers for Finite Fields" 38 (38): 796-800, 1991.
3 "Standard Specifications for Public key Cryptography" 2000.
4 C. W. Chiou, "Low-complexity finite field multiplier using irreducible trinomials" 39 (39): 1709-1711, 2003.
5 Chiou-Yng Lee, "Low complexity bit-parallel systolic multiplier over using irreducible trinomials" 150 (150): 39-42, 2003.
6 이찬호, "ECC 연산을 위한 가변 연산 구조를 갖는 정규기저 곱셈기와 역원기" 40 (40): 2003.
7 Sonnhak Kwon, "Compact linear systolic arrays for multiplication using a trinomial basis in for high speed cryptographic processors" 508-518, 2005.
8 Sonnhak Kwon, "Compact linear systolic arrays for multiplication using a trinomial basis in for high speed cryptographic processors" 508-518, 2005.
9 I. S. Hsu, "A comparison of VLSI Architecture of Finite Field Multipliers Using Dual IEEE Trans. on Computers" 37 (37): 735-739, 1988.
10 G. Orlando, "A Super-serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms" 232-239, 1999.
1 E. Mastrovito, "VLSI Architectures for Computation in Galois Fields" dept. of electrical eng. : 1991.
2 Chin-Liang Wang, "Systolic Array Implementation of Multipliers for Finite Fields" 38 (38): 796-800, 1991.
3 "Standard Specifications for Public key Cryptography" 2000.
4 C. W. Chiou, "Low-complexity finite field multiplier using irreducible trinomials" 39 (39): 1709-1711, 2003.
5 Chiou-Yng Lee, "Low complexity bit-parallel systolic multiplier over using irreducible trinomials" 150 (150): 39-42, 2003.
6 이찬호, "ECC 연산을 위한 가변 연산 구조를 갖는 정규기저 곱셈기와 역원기" 40 (40): 2003.
7 Sonnhak Kwon, "Compact linear systolic arrays for multiplication using a trinomial basis in for high speed cryptographic processors" 508-518, 2005.
8 Sonnhak Kwon, "Compact linear systolic arrays for multiplication using a trinomial basis in for high speed cryptographic processors" 508-518, 2005.
9 I. S. Hsu, "A comparison of VLSI Architecture of Finite Field Multipliers Using Dual IEEE Trans. on Computers" 37 (37): 735-739, 1988.
10 G. Orlando, "A Super-serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms" 232-239, 1999.
11 L.Adleman, "A Subexponential Algorithm for Discrete Logarithms over All Finite Fields Advances in Cryptography- CRYPTO 93" 147-158, 1993.