1 Z. Yang, "Technical review for Chinese future DTTB system" 1-6, 2010
2 Micron Technology, Inc, "SDRAM system-power calculator"
3 J. L. Ramsey, "Realization of optimum interleavers" 338-345, 1970
4 M. Liu, "Analysis and performance comparison of DVB-T and DTMB systems for terrestrial digital TV" 1399-1404, 2008
5 H. Yang, "An FPGA prototype of a forward error (FEC) decoder for ATSC digital TV" 387-395, 1999
6 Y.-N. Chang, "A multibank memory-based VLSI architecture of DVB symbol deinterleaver" 840-843, 2010
7 Y. Zhong, "A VLSI implementation of a FEC decoding system for DTMB(GB20600-2006) standard" 926-929, 2007
8 M. Rim, "A VLSI architecture for convolutional deinterleavers" 130-131, 1996
1 Z. Yang, "Technical review for Chinese future DTTB system" 1-6, 2010
2 Micron Technology, Inc, "SDRAM system-power calculator"
3 J. L. Ramsey, "Realization of optimum interleavers" 338-345, 1970
4 M. Liu, "Analysis and performance comparison of DVB-T and DTMB systems for terrestrial digital TV" 1399-1404, 2008
5 H. Yang, "An FPGA prototype of a forward error (FEC) decoder for ATSC digital TV" 387-395, 1999
6 Y.-N. Chang, "A multibank memory-based VLSI architecture of DVB symbol deinterleaver" 840-843, 2010
7 Y. Zhong, "A VLSI implementation of a FEC decoding system for DTMB(GB20600-2006) standard" 926-929, 2007
8 M. Rim, "A VLSI architecture for convolutional deinterleavers" 130-131, 1996