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    RISS 인기검색어

      KCI우수등재

      Survey on Recent Cryogenic Computing Research

      한글로보기

      https://www.riss.kr/link?id=A108011253

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      부가정보

      목차 (Table of Contents)

      • 요약
      • Abstract
      • 1. 서론
      • 2. 배경
      • 3. 극저온 MOSFET 소자 연구
      • 요약
      • Abstract
      • 1. 서론
      • 2. 배경
      • 3. 극저온 MOSFET 소자 연구
      • 4. 극저온 최적화 컴퓨팅 구성 요소 연구
      • 5. 기존 연구의 한계 및 향후 연구 방향
      • 6. 결론
      • References
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      참고문헌 (Reference)

      1 C. Celio, "The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor"

      2 L. Yuan, "Temperature dependence of magnetoresistance in magnetic tunnel junctions with different free layer structures" 73 (73): 2006

      3 M. Chang, "Technology comparison for large last-level caches(L3Cs) : Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM" 143-154, 2013

      4 Synopsys, "Synopsys dc ultra"

      5 K. Ishida, "SuperNPU : An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices" 58-72, 2020

      6 C. Vaca, "Study From Cryogenic to High Temperatures of the High-and Low-Resistance-State Currents of ReRAM Ni-HfO2-Si Capacitors" 63 (63): 1877-1883, 2016

      7 T. Kelly, "Some Like It Cold: Initial Testing Results for Cryogenic Computing Components" 1182 (1182): 2019

      8 E. Garzón, "Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures" 57 (57): 1-6, 2021

      9 R. R. Schaller, "Moore's law : past, present and future" 34 (34): 52-59, 1997

      10 H. Zhao, "Modeling of a standard 0. 35μm CMOS technology operating from 77K to 300K" 59 : 49-59, 2014

      1 C. Celio, "The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor"

      2 L. Yuan, "Temperature dependence of magnetoresistance in magnetic tunnel junctions with different free layer structures" 73 (73): 2006

      3 M. Chang, "Technology comparison for large last-level caches(L3Cs) : Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM" 143-154, 2013

      4 Synopsys, "Synopsys dc ultra"

      5 K. Ishida, "SuperNPU : An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices" 58-72, 2020

      6 C. Vaca, "Study From Cryogenic to High Temperatures of the High-and Low-Resistance-State Currents of ReRAM Ni-HfO2-Si Capacitors" 63 (63): 1877-1883, 2016

      7 T. Kelly, "Some Like It Cold: Initial Testing Results for Cryogenic Computing Components" 1182 (1182): 2019

      8 E. Garzón, "Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures" 57 (57): 1-6, 2021

      9 R. R. Schaller, "Moore's law : past, present and future" 34 (34): 52-59, 1997

      10 H. Zhao, "Modeling of a standard 0. 35μm CMOS technology operating from 77K to 300K" 59 : 49-59, 2014

      11 M. Shin, "Low temperature characterization of 14nm FDSOI CMOS devices" 29-32, 2014

      12 O. Semenov, "Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs : perspective of low temperature current testing" 33 (33): 985-994, 2002

      13 J. Yau, "Hybrid Cryogenic Memory Cells for Superconducting Computing Applications" 1-3, 2017

      14 "Google Data Centers Efficiency"

      15 E. Garzón, "Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study" 29 (29): 1319-1324, 2021

      16 X. Huang, "Forming-Free, Fast, Uniform, and High Endurance Resistive Switching From Cryogenic to High Temperatures in W/AlOx/Al2O3/Pt Bilayer Memristor" 41 (41): 549-552, 2020

      17 Y. Kim, "Flipping bits in memory without accessing them : An experimental study of DRAM disturbance errors" 361-372, 2014

      18 E. Garzón, "Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications" 20 : 123-128, 2021

      19 F. Ware, "Do superconducting processors really need cryogenic memories? : the case for cold DRAM" 183-188, 2017

      20 R. H. Dennard, "Design of ionimplanted MOSFET's with very small physical dimensions" 9 (9): 256-268, 1974

      21 I. Nagaoka, "Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic" 1-3, 2019

      22 F. Wang, "DRAM Retention at Cryogenic Temperatures" 1-4, 2018

      23 S. S. Tannu, "Cryogenic-DRAM based memory system for scalable quantum computers : a feasibility study" 189-195, 2017

      24 S. Resch, "Cryogenic PIM : Challenges & Opportunities" 20 (20): 74-77, 2021

      25 Y. Aiba, "Cryogenic Operation of 3D Flash Memory for New Applications and Bit Cost Scaling with 6-Bit per Cell(HLC)and Beyond" 1-3, 2021

      26 G. Lee, "Cryogenic Computer Architecture Modeling with Memory-Side Case Studies" 774-787, 2019

      27 G. Lee, "CryoGuard : A Near Refresh-Free Robust DRAM Design for Cryogenic Computing" 637-650, 2021

      28 I. Byun, "CryoCore : A Fast and Dense Processor Architecture for Cryogenic Computing" 335-348, 2020

      29 D. Min, "CryoCache : A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing" 449-464, 2020

      30 B. Patra, "Cryo-CMOS Circuits and Systems for Quantum Computing Applications" 53 (53): 309-321, 2018

      31 W. Ryan, "Channel codes: classical and modern" Cambridge university press 2009

      32 Y. Iwasa, "Case studies in superconducting magnets:design and operational issues" Springer Science &Business Media 2009

      33 K. Chen, "CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory" 33-38, 2012

      34 X. Xi, "Bsim4.3.0 mosfet model"

      35 Y. Aiba, "Bringing in Cryogenics to Storage : Characteristics and Performance Improvement of 3D Flash Memory" 1-4, 2021

      36 T. J. Dell, "A white paper on the benefits of chipkill-correct ECC for PC server main memory" 11 : 1997

      37 L. Lang, "A low temperature functioning CoFeB/MgO-based perpendicular magnetic tunnel junction for cryogenic nonvolatile random access memory" 116 (116): 2020

      38 I. Nagaoka, "A 48GHz 5. 6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic" 460-462, 2019

      39 W. H. Henkels, "A 4-Mb low-temperature DRAM" 26 (26): 1519-1529, 1991

      40 K. C. Chun, "A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches" 46 (46): 1495-1505, 2011

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      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2021 평가예정 계속평가 신청대상 (등재유지)
      2016-01-01 평가 우수등재학술지 선정 (계속평가)
      2015-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2002-01-01 평가 학술지 통합 (등재유지) KCI등재
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.19 0.19 0.19
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.2 0.18 0.373 0.07
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