Hybrid 8T SRAM 설계 방법에 관한 연구 = A Study on the Design Methodology for Hybrid 8T SRAM

국문 초록 (Abstract)

실리콘 기반 집적회로의 제조 공정이 물리적 한계에 가까워짐에 따라 이를 극복하기 위한 반도체 물질에 많은 관심이 집중되고있다. 탄소나노튜브(CNT)는 우수한 전기 수송 및 스케일링 특성을 가진 가장 경쟁력 있는 소재 중 하나로 많은 관심을 받고 있으며,이러한 CNT를 활용한 CNTFET은 차세대 반도체 소자로 많은 인기를 얻고 있다. 하지만, CNT를 웨이퍼 위에 일정한 방향과 간격으로 배치시키는 기술이 아직 충분히 성숙하지 않아 CNTFET만으로 필요한 모든 회로를 구성하기에는 어려움이 있다. 따라서,MOSFET과 CNTFET을 함께 사용하는 hybrid 구성에 관심이 커지고 있다. SRAM은 마이크로프로세서에서 캐시 역할을 하며 마이크로프로세서 성능에 중요한 영향을 미치는 회로블록이기 때문에 기존 SRAM을 hybrid 형태로 구현하고자 하는 연구가 꾸준히 진행되고 있다. 따라서, 본 논문에서는 기존의 hybrid 6T SRAM을 기반으로 hybrid 8T SRAM 디자인 방법에 대해 설명하고 두 회로 사이의 성능차에 대해 논의하고자 한다.

다국어 초록 (Multilingual Abstract)

As the production process for silicon-based integrated circuits approaches physical limits, a lot of attention isfocused on the new semiconductor materials to overcome these problems. Carbon NanoTubes(CNTs) are attractinga lot of interest as one of the most competitive materials with excellent electrical transport and scaling properties,and CNTFETs using CNTs are gaining popularity as next-generation semiconductor devices. However, since thetechnology to place CNTs in a certain direction and interval on the wafer is not yet mature enough, it is difficultto construct all necessary circuits with CNTFET only. So, there is increasing interest in a hybrid configurationusing MOSFET and CNTFET together. Because SRAM plays a role as a cache in microprocessors and is a criticalcircuit block influencing microprocessor performance, research to implement existing SRAM in a hybrid form issteadily progressing. Therefore, in this paper, we will explain the design method of hybrid 8T SRAM based on theexisting hybrid 6T SRAM and discuss the performance difference between the two circuits.

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