슈퍼스칼라 프로세서에서 효율적인 레지스터 사용 방법 = A Scheme to Use Register File Efficiently in Superscalar Processors

다국어 초록 (Multilingual Abstract)

In superscalar processors, the instruction-level parallelism is exploited using out-of-order issue and completion mechanism. Also, they must support restarting and recovering mechanism to handle precise interrupts and support register renaming and forwarding logic to resolve data dependencies. The most important thing in superscalar processors is the interrupt handling mechanism. The organization and performance of processors are largely influenced by methods to handle the interrupt. In dynamically scheduled superscalar processors using the reorder buffer, references of short live range variables may occur entirely within the reorder buffer.
This paper proposes an efficient register allocation algorithm that assigns buffer variables, which have not any exception in their live range, to entries in the reorder buffer. Also, it proposes a reorder buffer structure to handle the interrupt for the proposed register algorithm.