설계자동화를 위한 VHDL Analyzer에 관한 연구 = A Study on the VHDL Analyzer for Design Automation

다국어 초록 (Multilingual Abstract)

This paper has developed the automation system for logic design, using widely available VHDL language as the standard hardware description language[1][8][9], which extracts the efficient FSM(Finite State Machine) List in automatic optimized synthesis for the practical ASIC hardware from the design technique of the register transfer level.
VHDL analysis process in this paper is similar to compiler process in software area, is partitioned into the VHDL parsing, the Behavioral transformation, the Basic block recognition, and the Dependency analysis, etc[5][7]. VHDL parsing resulted in the FSM (Finite State Machine) List efficient in Data Path and Control Path synthesis for logic design with creating the intermediate code in AST(Abstract Syntax Tree) for the intermediate symbol table.

목차 (Table of Contents)

• Ⅰ. 서론
• Ⅱ. 설계자동화를 위한 VHDL 기술사양
• 1. VHDL 언어의 특징
• 2. 설계자동화를 위한 VHDL 지원 환경
• 3. 설계자동화를 위한 VHDL 부분 사양의 결정
• Ⅲ. 설계자동화를 위한 VHDL 언어의 Parser 설계 및 구현
• 1. VHDL Analyzer 구현
• 2. VHDL 모델링
• 3. VHDL Parser 구현 및 설계
• Ⅳ. 결론
• 참고문헌