Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs

다국어 초록 (Multilingual Abstract)

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixedmode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the VDD and VSS buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

목차 (Table of Contents)

• Abstract
• Ⅰ. INTRODUCTION
• Ⅱ. ESD PROTECTION SCHEME AND MIXEDMODE SIMULATION SETUP
• Ⅲ. DISCHARGE CHARACTERISTICS WITH THE MODIFIED DEVICE STRUCTURE
• Ⅳ. ADDITIONAL STRUCTURE OPTIMIZATION
• Ⅴ. CONCLUSIONS
• REFERENCES