Device and Process Design Based on Functional Oxide Thin Films for Advanced Memory Applications

다국어 초록 (Multilingual Abstract)

In this work, we present an integrated approach for implementing high-performance and high- reliability memory technology by precisely controlling the material-specific electrical properties of functional oxide thin films and applying them to the structural design of memory devices. In particular, representative oxide materials such as HfO2, Al2O3, and InGaZnO (IGZO) were applied to various roles such as ferroelectric layers, insulating layers, and channel layers, respectively, and the memory performance parameters such as charge storage characteristics, bias stability, and data retention characteristics of the devices were experimentally verified by controlling the process conditions and the stacked structure, and the possibility of applying them to memory devices was verified. First, the crystallization behavior and ferroelectric characteristic changes were analyzed by introducing an Al2O3 capping layer on an undoped HfO2 thin film. The crystal phase transition and polarization switching characteristics according to the temperature conditions of the HfO2 atomic layer deposition (ALD) process were evaluated, and it was confirmed that the polarization characteristics, leakage current, and endurance of the ferroelectric capacitor with the metal- insulator-ferroelectric-metal (MIFM) structure were significantly improved through the stabilization of the ferroelectric phase, which is the orthorhombic phase (o-phase). This suggests an effective methodology that can implement excellent ferroelectric characteristics only through interface control without separate doping. Second, by designing the IGZO thin film as a double-layer (DL) structure and depositing it with different oxygen partial pressures (PO2) during the sputtering process, we attempted to improve the performance in a 2-transistor-0-capacitor (2T0C) DRAM cell. The heterogeneous interface formed between the upper and lower IGZO layers served as an additional conduction path, and the storage efficiency and retention time were increased by advantageously utilizing the parasitic capacitance through geometric optimization of the active area. Through this, we propose a performance improvement method of 2T0C DRAM cells by combining structural design and material control. Finally, we designed a HfO2/Al2O3 nanolaminate gate insulator (GI) structure to secure electrical reliability while utilizing high-K dielectrics in the thin film transistor (TFT) constituting the 2T0C DRAM cell. By periodically laminating HfO2 and Al2O3 through a 150 °C ALD process, we simultaneously achieved crystallization suppression and interface defect reduction, which led to low-voltage operation and improved bias stress stability. When applied to an actual 2T0C DRAM cell, it was successfully verified by showing excellent long-term retention behavior. These results provide guidelines for the design of insulators for low-temperature oxide transistor- based memories.

목차 (Table of Contents)

• Table Contents iv
• Figure Contents v
• Abstract x
• 1. Introduction 1
• 1.1 Motivations 1
• 1.2 Research objects 3
• 1.3 Outline of this work 5
• 2. Technical Backgrounds 7
• 2.1 Atomic layer deposition (ALD) 7
• 2.2 Sputtering deposition 9
• 2.3 HfO2-based ferroelectrics 11
• 2.4 Oxide semiconductor (OS) 13
• 2.5 2-transistor 0-capacitor (2T0C) DRAM cell 15
• 3. Al2O3 Capping Effect in Undoped HfO2 Capacitor 17
• 3.1 Introduction 17
• 3.2 Device fabrication 19
• 3.3 Physical and chemical properties of HfO2 thin films 21
• 3.3.1 Phase evolution and crystallization behavior 21
• 3.3.2 Thickness and density variation 24
• 3.3.3 Grain size by film growth 26
• 3.3.4 Oxygen-related defect characteristics 29
• 3.4 Device characteristics of MIFM capacitor 32
• 3.4.1 Polarization-voltage (P-V) hysteresis 32
• 3.4.2 Leakage current density and endurance 35
• 3.5 Ferroelectric switching dynamics of HfO2 thin films 37
• 3.5.1 Double-pulse switching measurements 37
• 3.5.2 Switching characteristics 41
• 3.6 Conclusion 45
• 4. 2T0C DRAM Cells Using Double-Layer IGZO and Geometry Modulation 46
• 4.1 Introduction 46
• 4.2 Device fabrication 48
• 4.3 Device characteristics of single transistors 51
• 4.3.1 Transfer and output characteristics 51
• 4.3.2 Bias stress reliability evaluation 53
• 4.4 2T0C DRAM cell memory characteristics 57
• 4.4.1 Optimization of active geometry 57
• 4.4.2 Memory write speed and retention characteristics 59
• 4.5 Conclusion 62
• 5. 2T0C DRAM Cells Using Interface-Engineered HfO2/Al2O3 Nanolaminate Film 63
• 5.1 Introduction 63
• 5.2 Device fabrication 65
• 5.3 HfO2/Al2O3 nanolaminate film properties 67
• 5.3.1 Crystallinity and interfacial characteristics 67
• 5.3.2 Depth-dependent defect characteristics 69
• 5.3.3 MIM Capacitor characteristics 73
• 5.4 Device characteristics of single transistors and 2T0C DRAM cells 75
• 5.4.1 Transfer characteristics 75
• 5.4.2 Bias stress reliability evaluation 77
• 5.4.3 Retention characteristics 79
• 5.5 Conclusion 81
• 6. Conclusion 82
• 6.1 Main results and summary 82
• 6.2 Future perspectives 85
• References 87
• List of publication 97
• List of presentation 98
• List of awards 99
• 국문 초록 100