접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계

참고문헌 (Reference)

1 문용삼, "차동 연결된 Varactor를 이용한 6Gbps CMOS 피드포워드 이퀄라이저" 대한전자공학회 46 (46): 64-70, 2009

2 M.-J. E. Lee, "Low-power, area efficient, high speed I/O circuit techniques" 35 : 1591-1599, 2000

3 M.-J. E. Lee, "Low-power area-efficient highspeed I/O circuit techniques" 35 (35): 1591-1599, 2000

4 Jeeradit, M, "Characterizing sampling aperture of clocked comparators" 68-69, 2008

5 Eun-Ji Choi, "A Low-Swing AC- and DC-Coupled Voltage-Mode Driver with Pre-emphasis" 2011

6 Jun-Han Bae, "A Low-Power Dual-PFD Phase-Rotating PLL with a PFD Controller for 5Gb/s Serial Links" 2012

7 F. Yang, "A CMOS low-power multiple2.5-3.125-Gb/s serial link macrocell for high IObandwidth network ICs" 37 : 1813-1821, 2002

8 Beukema, T., "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization" 40 (40): 2633-2645, 2005

9 Wong, K.-L.J., "A 27-mW 3.6-gb/s I/O transceiver" 39 (39): 602-612, 2004

10 Poulton, J., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS" 42 (42): 2745-2757, 2007

11 Fukuda, K., "A 12.3-mW 12.5-Gb/s Complete Transceiver" 45 (45): 2838-2849, 2010

12 Kaviani, Kambiz, "A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration" 132-134, 2012

13 Youngkyun Jeong, "0.37mW/Gb/s Low Power SLVS Transmitter for Battery Powered Applications" 2012