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      KCI등재 SCIE SCOPUS

      Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

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      https://www.riss.kr/link?id=A103680447

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      다국어 초록 (Multilingual Abstract)

      In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technolog...

      In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10° to 20° is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

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      참고문헌 (Reference)

      1 V. Zyuban, "Unified methodology for resolving powerperformance tradeoffs at the microarchitectural and circuit levels" ACM 166-171, 2002

      2 J. P. Duarte, "Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs" 135-138, 2013

      3 E. J. Nowak, "Turning silicon on its edge double gate CMOS/FinFET technology" 20 (20): 20-31, 2004

      4 J. Slotboom, "The pn-product in silicon" 20 (20): 279-283, 1977

      5 M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era" 1-1, 2011

      6 "Sentaurus TCAD User Guide, Ver. H-2013.03"

      7 W. Kehuey, "Performance advantage and energy saving of triangular-shaped FinFETs" 143-146, 2013

      8 R. Giacomini, "Non-Vertical Sidewall Angle Influence on Triple-Gate FinFETs Corner Effects" 6 (6): 381-386, 2007

      9 Y. Taur, "Modern VLSI devices" Cambridge Univ. Press 2009

      10 D. Zhang, "Modeling of photoresist erosion in plasma etching processes" 30 (30): 114-115, 2002

      1 V. Zyuban, "Unified methodology for resolving powerperformance tradeoffs at the microarchitectural and circuit levels" ACM 166-171, 2002

      2 J. P. Duarte, "Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs" 135-138, 2013

      3 E. J. Nowak, "Turning silicon on its edge double gate CMOS/FinFET technology" 20 (20): 20-31, 2004

      4 J. Slotboom, "The pn-product in silicon" 20 (20): 279-283, 1977

      5 M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era" 1-1, 2011

      6 "Sentaurus TCAD User Guide, Ver. H-2013.03"

      7 W. Kehuey, "Performance advantage and energy saving of triangular-shaped FinFETs" 143-146, 2013

      8 R. Giacomini, "Non-Vertical Sidewall Angle Influence on Triple-Gate FinFETs Corner Effects" 6 (6): 381-386, 2007

      9 Y. Taur, "Modern VLSI devices" Cambridge Univ. Press 2009

      10 D. Zhang, "Modeling of photoresist erosion in plasma etching processes" 30 (30): 114-115, 2002

      11 P. Clarke, "Intel’s FinFETs are less fin and more triangle"

      12 X. Wu, "Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET" 52 (52): 63-68, 2005

      13 D. Sinitsky, "High field hole velocity and velocity overshoot in silicon inversion layers" 18 (18): 54-56, 1997

      14 "HSPICE, Ver. H-2013.03"

      15 S. Sinha, "Exploring sub-20nm FinFET design with predictive technology models" 283-288, 2012

      16 C.-H. Lin, "Channel doping impact on finfets for 22nm and beyond" 15-16, 2012

      17 R. Huang, "Challenges of 22 nm and beyond CMOS technology" 52 (52): 1491-1533, 2009

      18 M.-h. Chi, "Challenges in Manufacturing FinFET at 20nm node and beyond" Technology Development, Global Foundries 2012

      19 M. V. Dunga, "BSIM-MG: A versatile multi-gate FET model for mixed-signal design" 60-61, 2007

      20 D. Klaassen, "A unified mobility model for device simulation-I. Model equations and concentration dependence" 35 (35): 953-959, 1992

      21 C. Lombardi, "A physically based mobility model for numerical simulation of nonplanar devices" 7 (7): 1164-1171, 1988

      22 C. Auth, "A 22nm high performance and lowpower CMOS technology featuring fullydepleted tri-gate transistors, self-aligned contacts and high density MIM capacitors" 131-132, 2012

      23 Intel Corporation, "3-D, 22nm: New Technology Delivers An Unprecedented Combination of Performance and Power Efficiency"

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
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