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RISS 인기검색어

A Constructing Theory of Multiple-Valued Logic Functions based on the Exclusive-OR Minimization Technique and Its Implementation

한글로보기

https://www.riss.kr/link?id=A3351597

저자

Park, Dong Young (Department of Electronics Engineering, Inha University) ; Kim, Heung Soo (Department of Electronics Engineering, Inha University)
발행기관
대한전자공학회(The Korean Institute of Telematics and Electronics)
학술지명
HICEC:Harbin International Conference on Electronics and Computers
권호사항

Vol.1 No.1 [1992]
발행연도
1992
작성언어
English
KDC
569.000
자료형태
학술저널
발행기관 URL
http://www.ieek.or.kr
수록면

24-28(5쪽)
제공처
DBpia

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다국어 초록 (Multilingual Abstract)

This paper presents an algorithm of reducing the literal product terms(LPT) to minimize MVL functions expressed in exclusive-sum-of-literal-product(ESOLP) from by inserting LPTs and making LPT-loops artificially. The insertable LPTs are derived from the distance calculation method between adjacent LPTs. Since ESOLP-expressed functions can be formulated in two-level MIN/EXOR structure, a 4-valued MIN/EXOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions. Finally, PSPICE simulation results for the dynamic CMOS implementation of a 4-valued, 2-product-line-input, 2-output PLA have been also presented.

번역하기

This paper presents an algorithm of reducing the literal product terms(LPT) to minimize MVL functions expressed in exclusive-sum-of-literal-product(ESOLP) from by inserting LPTs and making LPT-loops artificially. The insertable LPTs are derived from t...

This paper presents an algorithm of reducing the literal product terms(LPT) to minimize MVL functions expressed in exclusive-sum-of-literal-product(ESOLP) from by inserting LPTs and making LPT-loops artificially. The insertable LPTs are derived from the distance calculation method between adjacent LPTs. Since ESOLP-expressed functions can be formulated in two-level MIN/EXOR structure, a 4-valued MIN/EXOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions. Finally, PSPICE simulation results for the dynamic CMOS implementation of a 4-valued, 2-product-line-input, 2-output PLA have been also presented.