효율적인 단정도/배정도 승산을 위한 이중모드 승산기 = A Dual Mode Multiplier for Efficient Single/Double-Precision Multiplication

다국어 초록 (Multilingual Abstract)

High-speed/low-power/low-cost multipliers play an important role in micro-processors and digital signal processors because multiplier core not only occupies a signigicant percentage of the silicon area, but also limits the overall performance. This paper describes a design of dual mode multiplier (DMM) that performs single- and double-precision multiplications using hardware required for single-precision multiplication. We propose an efficient algorithm which partitions a double-precision multiplication into four single-precision sub-multiplications and then computes them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces hardware complexity required for double-precision multiplication by about one third at the expense of increased latency. The DMM has been designed using a 0.25-㎛ 5-metal CMOS technology, and contains about 25,000 transistors on the area of about 0.77×0.40㎟. The HSPICE simulation results show that the DMM core can safely operate with 150-MHz clock at 2.5-V, and the estimated power dissipation is about 110-mW at double-precision mode.