Gate-All-Around(GAA) nanosheet FETs are considered promising next-generation transistors. However, source/draincontact resistance remains a critical bottleneck in the sub-3 nm regime due to Fermi-level pinning in conventionalmetal-semiconductor (MS) c...
Gate-All-Around(GAA) nanosheet FETs are considered promising next-generation transistors. However, source/draincontact resistance remains a critical bottleneck in the sub-3 nm regime due to Fermi-level pinning in conventionalmetal-semiconductor (MS) contacts. This paper proposes a metal-insulator-semiconductor (MIS) source/draincontact structure with an ultrathin interlayer and optimizes the interlayer material and thickness using SentaurusTCAD simulations. A ZnO interlayer with a thickness of 2 nm is identified as the optimal condition. The optimizedMIS GAA nanosheet FET achieves approximately 81.6% reduction in static power and 242% improvement inswitching performance, demonstrating simultaneous enhancement of power, performance, area.