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      반도체 산업에서 생산용량을 고려한 오더-로트 페깅기반의 납기약속 방법의 정합성 향상에 대한 연구 = On-time Production and Delivery Improvements through the Demand-Lot Pegging Framework for a Semiconductor Business

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      https://www.riss.kr/link?id=A103679684

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      다국어 초록 (Multilingual Abstract)

      This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business(memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-timeproduction and delivery. However existing pegging system and researches do not consider capacity limit on bottleneck steps. This paper presents an order-lot pegging algorithm for assigning a lot to an order considering quality constraints of each lotand capacity of bottleneck steps along the entire FAB. As a result, a quick and accurate response can be provided to customerorder enquiries and pegged lot lists for each promised orders can be shown transparently and short or late orders can be detectedbefore fixing the order.
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      This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business(memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-time...

      This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business(memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-timeproduction and delivery. However existing pegging system and researches do not consider capacity limit on bottleneck steps. This paper presents an order-lot pegging algorithm for assigning a lot to an order considering quality constraints of each lotand capacity of bottleneck steps along the entire FAB. As a result, a quick and accurate response can be provided to customerorder enquiries and pegged lot lists for each promised orders can be shown transparently and short or late orders can be detectedbefore fixing the order.

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      참고문헌 (Reference)

      1 조남욱, "반도체 산업의 협업전략계획에 관한 연구" 한국산업경영시스템학회 28 (28): 139-145, 2005

      2 Lim, S. -K., "Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities" 52 : 3710-3724, 2004

      3 Ng, T. S., "Semiconductor lot allocation using robust optimization" 205 : 557-570, 2010

      4 Kim, J.-G., "Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process" 63 : 1258-1270, 2012

      5 Steiner, G., "Optimal level schedules in mixed-model, multi-level JIT assembly systems with pegging" 95 : 38-52, 1996

      6 Wu, T.W., "Modular demand and supply pegging mechanism for semiconductor foundry" 325-328, 2003

      7 Fowler, J., "Measurement and improvement of manufacturing capacities(MIMAC) : Final report" SEMATECH 1995

      8 Knutson, K., "Lot-to-order matching for a semiconductor assembly and test facility" 31 : 1103-1111, 1999

      9 Fowler, J., "Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility" 38 : 1841-1853, 2000

      10 Choi, B.K., "Capacity-filtering algorithms for finite-capacity planning of a flexible flow Line" 47 (47): 3363-3386, 2009

      1 조남욱, "반도체 산업의 협업전략계획에 관한 연구" 한국산업경영시스템학회 28 (28): 139-145, 2005

      2 Lim, S. -K., "Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities" 52 : 3710-3724, 2004

      3 Ng, T. S., "Semiconductor lot allocation using robust optimization" 205 : 557-570, 2010

      4 Kim, J.-G., "Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process" 63 : 1258-1270, 2012

      5 Steiner, G., "Optimal level schedules in mixed-model, multi-level JIT assembly systems with pegging" 95 : 38-52, 1996

      6 Wu, T.W., "Modular demand and supply pegging mechanism for semiconductor foundry" 325-328, 2003

      7 Fowler, J., "Measurement and improvement of manufacturing capacities(MIMAC) : Final report" SEMATECH 1995

      8 Knutson, K., "Lot-to-order matching for a semiconductor assembly and test facility" 31 : 1103-1111, 1999

      9 Fowler, J., "Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility" 38 : 1841-1853, 2000

      10 Choi, B.K., "Capacity-filtering algorithms for finite-capacity planning of a flexible flow Line" 47 (47): 3363-3386, 2009

      11 Carlyle, M., "Bin covering algorithms in the second stage of the lot to order matching problem" 52 : 1232-1243, 2001

      12 Bang, J. -Y., "A due-date based algorithm for order-lot pegging in a semiconductor wafer fabrication facility" 21 : 209-216, 2008

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      2018-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2015-01-01 평가 등재학술지 유지 (등재유지) KCI등재
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      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.34 0.34 0.3
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
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