1 조남욱, "반도체 산업의 협업전략계획에 관한 연구" 한국산업경영시스템학회 28 (28): 139-145, 2005
2 Lim, S. -K., "Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities" 52 : 3710-3724, 2004
3 Ng, T. S., "Semiconductor lot allocation using robust optimization" 205 : 557-570, 2010
4 Kim, J.-G., "Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process" 63 : 1258-1270, 2012
5 Steiner, G., "Optimal level schedules in mixed-model, multi-level JIT assembly systems with pegging" 95 : 38-52, 1996
6 Wu, T.W., "Modular demand and supply pegging mechanism for semiconductor foundry" 325-328, 2003
7 Fowler, J., "Measurement and improvement of manufacturing capacities(MIMAC) : Final report" SEMATECH 1995
8 Knutson, K., "Lot-to-order matching for a semiconductor assembly and test facility" 31 : 1103-1111, 1999
9 Fowler, J., "Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility" 38 : 1841-1853, 2000
10 Choi, B.K., "Capacity-filtering algorithms for finite-capacity planning of a flexible flow Line" 47 (47): 3363-3386, 2009
1 조남욱, "반도체 산업의 협업전략계획에 관한 연구" 한국산업경영시스템학회 28 (28): 139-145, 2005
2 Lim, S. -K., "Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities" 52 : 3710-3724, 2004
3 Ng, T. S., "Semiconductor lot allocation using robust optimization" 205 : 557-570, 2010
4 Kim, J.-G., "Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process" 63 : 1258-1270, 2012
5 Steiner, G., "Optimal level schedules in mixed-model, multi-level JIT assembly systems with pegging" 95 : 38-52, 1996
6 Wu, T.W., "Modular demand and supply pegging mechanism for semiconductor foundry" 325-328, 2003
7 Fowler, J., "Measurement and improvement of manufacturing capacities(MIMAC) : Final report" SEMATECH 1995
8 Knutson, K., "Lot-to-order matching for a semiconductor assembly and test facility" 31 : 1103-1111, 1999
9 Fowler, J., "Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility" 38 : 1841-1853, 2000
10 Choi, B.K., "Capacity-filtering algorithms for finite-capacity planning of a flexible flow Line" 47 (47): 3363-3386, 2009
11 Carlyle, M., "Bin covering algorithms in the second stage of the lot to order matching problem" 52 : 1232-1243, 2001
12 Bang, J. -Y., "A due-date based algorithm for order-lot pegging in a semiconductor wafer fabrication facility" 21 : 209-216, 2008