Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

다국어 초록 (Multilingual Abstract)

In this paper, simple but very effectivetechniques to suppress subthreshold hump effect forhigh-voltage (HV) complementary metal-oxidesemiconductor(CMOS) technology are presented.
Two methods are proposed to suppress subthresholdhump effect using a simple layout modificationapproach. First, the uniform gate oxide method isbased on the concept of an H-shaped gate layoutdesign. Second, the gate work function controlmethod is accomplished by local ion implantation. Forour experiments, 0.18 μm 20 V class HV CMOStechnology is applied for HV MOSFETs fabrication.
From the measurements, both proposed methods arevery effective for elimination of the inverse narrowwidth effect (INWE) as well as the subthreshold hump

참고문헌 (Reference)

1 L. A. Akers, "The inverse-narrow-width effect" ED-7 (ED-7): 419-421, 1986

2 A. Bryant, "The currentcarrying corner inherent to trench isolation" 14 (14): 412-414, 1993

3 M. Nandakumar, "Shallow trench isolation for advanced ULSI CMOS technologies" 133-136, 1998

4 J. Lee, "Novel cell transistor using retracted Si3N4-liner STI for the improvement of data retention time in gigabit density DRAM and beyond" 48 (48): 1152-1158, 2001

5 K. Benaissa, "New cost-effective integration schemes enabling analog and highvoltage design in advanced CMOS SOC technologies" 221-222, 2010

6 M. J. M. Pelgrom, "Matching properties of MOS transistors" 24 (24): 1433-1440, 1989

7 J. Pimbley, "MOSFET scaling limits determined by subthreshold conduction" 36 (36): 1711-1721, 1989

8 T. Oishi, "Isolation edge effect depending on gate length of MOSFET’s with various isolation structures" 47 (47): 822-827, 2000

9 R. A. Bianchi, "High voltage devices integration into advanced CMOS technologies" 137-140, 2008

10 E. K. C. Tee, "High voltage NMOS double hump prevention by using baseline CMOS p-well implant" 289-293, 2010

11 C.-P. Chang, "Enabling STI for 0.1 μm technologies and beyond" 161-162, 1999

12 M.-J. Chen, "Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling" 31 (31): 259-262, 1996

13 E. Augendre, "Controlling STIrelated parasitic conduction in 90 nm CMOS and below" 507-510, 2002

14 N. Shigyo, "Analysis of an anomalous subthreshold current in a fully recessed oxide MOSFET using a three-dimensional device simulator" ED- 32 (ED- 32): 441-445, 1985

15 K. Horita, "Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 μm pitch isolation and beyond" 178-179, 2000

16 T. Uhlig, "A18 - a novel 0.18 μm smart power SOC IC technology for automotive applications" 237-240, 2007

17 J. Kim, "A shallow trench isolation using Nitric Oxide (NO)-annealed wall oxide to suppress inverse narrow width effect" 21 (21): 575-577, 2000

18 B.-C. Park, "A novel fermi level controlled high voltage transistor preventing sub-threshold hump" 313-316, 2008

19 G. Fuse, "A new isolation method with boron-implanted sidewalls for controlling narrow-width effect" ED-34 (ED-34): 356-360, 1987