Built-in Self-Test를 위한 VLSI 회로의 응답 압축기 설계 = A New Response Compactor of VLSI Circuits for Built-In self-test

다국어 초록 (Multilingual Abstract)

This paper proposes an algorithm for designing efficient space response compactors for built-in self-testing of VLSI circuits. This algorithm can be applied independently from the structure of circuits under test.
In conventional space response compactors, high hardware overhead is required and fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed algorithm of designing space response compactors reduces hardware overheads without reducing the fault coverage. Also, the algorithm can be applied even to general N-input logic gate, and the most efficient space response compactor can be designed considering the characteristics of output sequence from the circuit under test.
The proposed algorithm is implemented in C on a SUN SPARC 20 workstation and the experimental results on ISCAS'85 benchmark circuits with pseudorandom patterns generated by LFSR are obtained. The results show the efficiency and validity of the algorithm.

목차 (Table of Contents)

• I. 서 론
• II. 이론적 배경
• III. 프로그램이 가능한 공간 응답 압축기
• IV. 실험 결과
• V. 결 론