In this paper, TEP bus is proposed for implementation of Intel 8086-based multiprocessor system on a timeshared bus. The DPMC and the arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from ...
In this paper, TEP bus is proposed for implementation of Intel 8086-based multiprocessor system on a timeshared bus. The DPMC and the arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from the system bus. Dynamic priority scheme is selected for the arbitration algorithm of system bus arbiter. The proposed system bus is modeled by Petri-net for simulation.