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      지역성을 이용한 하이브리드 메모리 페이지 교체 정책 = Page Replacement Policy of DRAM&PCM Hybrid Memory Using Two Locality

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      https://www.riss.kr/link?id=A103316174

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      다국어 초록 (Multilingual Abstract)

      To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.
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      To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, page...

      To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

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      참고문헌 (Reference)

      1 정보성, "저전력 NAND 플래시 메모리를 위한 필터 버퍼의 효율성 분석" 대한임베디드공학회 7 (7): 201-207, 2012

      2 N. Nethercote, "Valgrind: A Program Supervision Framwork" 89 (89): 44-66, 2003

      3 K. Park, "Selective Data Buffering Module for Unified Hybrid Storage System" 173-178, 2015

      4 M. K. Qureshi, "Scalable High Performance Main Memory System Using Phase Change Memory Technology" 37 (37): 24-33, 2009

      5 G. Dhiman, "PDRAM:A Hybrid PRAM and DRAM Main Memory System" 664-669, 2009

      6 "Next Generation Nonvolatile Memory Semiconductor Technology Trend"

      7 M. Lee, "M-CLOCK:Migration-optimized Page Replacement Algorithm for Hybrid DRAM and PCM Memory Architecture" 2001-2006, 2015

      8 "HD Tune Pro"

      9 Y. Xie, "Future Memory and Interconnect Technologies" 964-969, 2013

      10 S. Im, "Differentiated Space Allocation for Wear Leveling on Phase-change Memory-based Storage Device" 60 (60): 45-51, 2014

      1 정보성, "저전력 NAND 플래시 메모리를 위한 필터 버퍼의 효율성 분석" 대한임베디드공학회 7 (7): 201-207, 2012

      2 N. Nethercote, "Valgrind: A Program Supervision Framwork" 89 (89): 44-66, 2003

      3 K. Park, "Selective Data Buffering Module for Unified Hybrid Storage System" 173-178, 2015

      4 M. K. Qureshi, "Scalable High Performance Main Memory System Using Phase Change Memory Technology" 37 (37): 24-33, 2009

      5 G. Dhiman, "PDRAM:A Hybrid PRAM and DRAM Main Memory System" 664-669, 2009

      6 "Next Generation Nonvolatile Memory Semiconductor Technology Trend"

      7 M. Lee, "M-CLOCK:Migration-optimized Page Replacement Algorithm for Hybrid DRAM and PCM Memory Architecture" 2001-2006, 2015

      8 "HD Tune Pro"

      9 Y. Xie, "Future Memory and Interconnect Technologies" 964-969, 2013

      10 S. Im, "Differentiated Space Allocation for Wear Leveling on Phase-change Memory-based Storage Device" 60 (60): 45-51, 2014

      11 A. N. Jacobvite, "Coset Coding to Extend the Lifetime of Memory" 222-233, 2013

      12 S. Lee, "CLOCKDWF:A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architecture" 63 (63): 2187-2200, 2013

      13 R. Maddah, "CAFO: Cost Aware Flip Optimization for Asymmetric Memoryes" 320-330, 2015

      14 S. Mittal, "A Survey of Software Techniques for Using Non-volatile Memoryes for Storage and Main Memory Systems" 27 (27): 1537-1550, 2016

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2028 평가예정 재인증평가 신청대상 (재인증)
      2022-01-01 평가 등재학술지 유지 (재인증) KCI등재
      2019-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2016-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2014-07-03 학술지명변경 외국어명 : Journal of IEMEK -> IEMEK Journal of Embedded Systems and Applications KCI등재
      2012-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2011-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2009-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.27 0.27 0.22
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.22 0.18 0.415 0.07
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