1 N. Kumar, "performance assessment of charge plasma based cylindrical GAA vertical nanowire TFET with impact of interface trap charge"" 66 : 4453-4460, 2019
2 D. Munteanu, "Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices" 47 : 1219-1225, 2003
3 R. Chaujar, "TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layereded gate architecture, Part II: Analog and large signal performance evaluation" 46 (46): 645-655, 2009
4 V. H. Nguyen, "Quantum modeling of the carrier mobility in FDSOIDevices" 61 (61): 3096-3102, 2014
5 M. Niquet, "Quantum calculations of the carrier mobility: methodology, matthiessen’s rule, and comparison with semi-classical approaches" 115 (115): 054512-, 2014
6 M. A. Raushan, "Performance enhancment of junctionless tunnel fi eld eff ect transistor using dual-k spacers" 13 : 912-920, 2018
7 Prateek kumar, "Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Eff ect Transistor" springer 2019
8 J. P. Colinge, "Nanowire transistors without junctions" 5 (5): 225-229, 2010
9 ROGER LAKE, "NON-EQUILIBRIUM GREEN’S FUNCTIONS IN SEMICONDUCTOR DEVICE MODELING" WORLD SCIENTIFIC 143-158, 2003
10 A. S. Mayrov, "Micrometer scale ballistic transport in encapsulated graphene at room temperature" 11 : 2396-2399, 2011
1 N. Kumar, "performance assessment of charge plasma based cylindrical GAA vertical nanowire TFET with impact of interface trap charge"" 66 : 4453-4460, 2019
2 D. Munteanu, "Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices" 47 : 1219-1225, 2003
3 R. Chaujar, "TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layereded gate architecture, Part II: Analog and large signal performance evaluation" 46 (46): 645-655, 2009
4 V. H. Nguyen, "Quantum modeling of the carrier mobility in FDSOIDevices" 61 (61): 3096-3102, 2014
5 M. Niquet, "Quantum calculations of the carrier mobility: methodology, matthiessen’s rule, and comparison with semi-classical approaches" 115 (115): 054512-, 2014
6 M. A. Raushan, "Performance enhancment of junctionless tunnel fi eld eff ect transistor using dual-k spacers" 13 : 912-920, 2018
7 Prateek kumar, "Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Eff ect Transistor" springer 2019
8 J. P. Colinge, "Nanowire transistors without junctions" 5 (5): 225-229, 2010
9 ROGER LAKE, "NON-EQUILIBRIUM GREEN’S FUNCTIONS IN SEMICONDUCTOR DEVICE MODELING" WORLD SCIENTIFIC 143-158, 2003
10 A. S. Mayrov, "Micrometer scale ballistic transport in encapsulated graphene at room temperature" 11 : 2396-2399, 2011
11 Naveen Kumar, "Low voltage charge-plasma based dopingless Tunnel Field Effect Transistor: analysis and optimization" Springer Science and Business Media LLC 26 (26): 1343-1350, 2020
12 T. Roy, "Dual-gated MoS2/WSe2 van der waals tunnel diodes and transistors"" 9 : 207-2079, 2015
13 M. Jagadesh Kumar, "Doping-less tunnel fi eld eff ect transistor : design and investigation" 60 (60): 3285-3290, 2013
14 N. Kumar, "Design and investigation of charge-plasma based work function engineered dualmetal-heterogeneous gate SiSi0.55Ge0.45 GAA-cylindrical NWTFET for ambipolar analysis" 66 (66): 1468-1474, 2019
15 Choi Woo Young, "Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs)" 나노기술연구협의회 3 (3): 1-15, 2016
16 S. O. Koswatta, "D.E. performance comparison between tunneling transistors and conventional MOSFETS" 56 (56): 456-465, 2009
17 I. Yang, "Back-Gated CMOS on SOIAS for dynamic threshold voltage control"" 44 : 822-, 1997
18 "ATLAS Device Simulation Software"