As the device geometry shrinks to the deep submicron region, chemical mechanical polishing(CMP) planarization become a more
essential technique of advanced ULSI process. Also, CMP process was required for the global planarization of inter-metal
diel...
As the device geometry shrinks to the deep submicron region, chemical mechanical polishing(CMP) planarization become a more
essential technique of advanced ULSI process. Also, CMP process was required for the global planarization of inter-metal
dielectric(IMD), inter-level dielectric(ILD) layers and interconnections with free-defect. Especially, the complete global
planarization of IMD, ILD and interconnections can be achieved only with the CMP process. However, as the IMD and ILD layer
gets thinner, several problems were found in the CMP process. It does have various problems such as dishing effect, torn
oxide defects and nitride residues in oxide. So, it leads to severe circuit failure, which affects yield.
In this paper, we studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization
of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft
and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the
defect level has shown little difference, however, the counts of scratch was defected less than 2 on JR111 pad. Through
the above result, we can select optimum polishing pad, so we can expect the improvement of throughput and device yield.