Digital logic and microprocessors

목차 (Table of Contents)

• CONTENTS
• 1 Between the Transistor and the High-Level Language = 1
• 1.1 Prior Perceptions = 1
• 1.2 A Spectrum of Digital Languages = 3
• 1.3 Control Flow = 6
• 1.4 Terms and Roles = 8
• 1.5 Some Digital History = 9
• 2 Boolean Algebra and Digital Logic = 11
• 2.1 Computer Logic Circuits = 11
• 2.2 Application of Logic Circuits = 15
• 2.3 Evaluation of Boolean Functions = 19
• 2.4 Boolean Algebra = 21
• 2.5 Simplification of Boolean Functions = 26
• 2.6 Boolean Algebra as an Algebra of Subsets = 28
• 2.7 On the History of the Algebra of Logic = 31
• Problems = 31
• References = 33
• 3 0, 1 : Binary Numbers or Logical Values? = 35
• 3.1 The Binary Number System = 35
• 3.2 Conversion between Bases = 37
• 3.3 Binary Coding of Decimal Digits = 40
• 3.4 Historical Note = 43
• Problems = 44
• References = 44
• 4 Simplification of Boolean Functions = 45
• 4.1 Standard Forms of Boolean Functions = 45
• 4.2 Karnaugh Map Representation of Boolean Functions = 52
• 4.3 Simplification of Functions on the Karnaugh Map = 60
• 4.4 Map Minimization of Product-of-Sums Expressions = 66
• 4.5 Incompletely Specified Functions = 68
• Problems = 71
• References = 73
• 5 Standard Digital Integrated Circuits = 75
• 5.1 Introduction = 75
• 5.2 Small-Scale Integrated Circuits = 79
• 5.3 Fan-out, Fan-in, and Noise Immunity = 80
• 5.4 Switching Delay in Logic Circuits = 85
• 5.5 Circuit Implementation with NAND and NOR Gates = 87
• 5.6 Multilevel All-NAND Realizations = 89
• 5.7 Reducing Package Counts in Multilevel Realizations = 94
• Problems = 98
• References = 101
• 6 Computer Arithmetic and Codes = 101
• 6.1 Introduction = 103
• 6.2 Conversion between Number Bases = 103
• 6.3 Coding of Information = 106
• 6.4 Parity = 111
• 6.5 Binary Arithmetic = 113
• 6.6 Implementation of Binary and BCD Addition = 117
• 6.7 Carry and Overflow = 121
• Problems = 123
• References = 126
• 7 Combinational MSI Parts, ROMS, and PLAs = 127
• 7.1 Perspective = 127
• 7.2 Combinational MSI Parts = 128
• 7.3 Read-Only Memory = 137
• 7.4 Chip-Select, Buses, and Three-State Switches = 144
• 7.5 Programmed Logic Arrays = 147
• 7.6 Describing Multiplexers with a Graphic Vector Notation = 153
• 7.7 Special Purpose MSI Parts = 154
• Problems = 158
• References = 161
• 8 Sequential Circuits = 163
• 8.1 Storage of Information = 163
• 8.2 Clocking = 166
• 8.3 Registers = 171
• 8.4 Memory Element Input Logic = 173
• 8.5 A First Design Example = 174
• 8.6 The J-K Flip-Flop = 177
• 8.7 Design of Counters = 181
• 8.8 MSI Registers and Counters = 187
• Problems = 195
• References = 197
• 9 Synthesis of State Machines = 199
• 9.1 A Language is Needed = 199
• 9.2 Standard Symbols for the ASM Chart = 200
• 9.3 Vending Machine Control = 204
• 9.4 From ASM Charts to Transition Tables = 208
• 9.5 Circuit Realization = 212
• 9.6 The State Diagram, an Alternative Notation = 216
• 9.7 Compatible States = 221
• Problems = 223
• References = 227
• 10 Register Transfer Design = 229
• 10.1 Generalized ASM Output = 229
• 10.2 ASM Chart Representation of a Control Unit = 231
• 10.3 Register Transfer Language(RTL) Notation = 233
• 10.4 Construction of a Data Unit from an RTL Description = 239
• 10.5 Timing of Connections and Transfers = 242
• 10.6 Sequencing of Control = 245
• 10.7 Combinational Logic and Conditional Transfers = 248
• 10.8 Graphical and RTL Bus Notation = 254
• 10.9 Timing Refinements in RTL Systems = 256
• 10.10 An RTL Design Example = 257
• Problems = 262
• References = 266
• 11 Small Computer Organization and Programming = 267
• 11.1 Introduction = 267
• 11.2 Central Processor and Memory Organization = 268
• 11.3 CPU Organization and Instruction Formats = 270
• 11.4 Fundamental Internal Sequence of a Single-Address Computer = 272
• 11.5 Transfer-of-Control and Register-Only Instructions = 279
• 11.6 Addition and Subtraction with Carry = 286
• 11.7 Commands That Affect Only the Flags = 290
• 11.8 Programming Procedures = 292
• Problems = 296
• 12 Addressing and Assembly Language = 301
• 12.1 Microprocessor Addressing = 301
• 12.2 Addressing Modes = 302
• 12.3 Assembly Language Programming = 311
• 12.4 More Programming = 316
• 12.5 Data Conversion, Decimal Arithmetic, and Subroutines = 320
• Problems = 330
• 13 Memory and Input／Output = 333
• 13.1 Memory Mapping = 333
• 13.2 Timing of Memory Operation = 338
• 13.3 Parallel Input／Output Interfacing = 340
• 13.4 Interactive Input／output = 346
• 13.5 Programming Time Delays = 355
• 13.6 Device Drivers = 359
• 13.7 Substituting Input Scanning for Combinational Logic = 366
• 13.8 Time-Sharing of Interface Ports = 370
• Problems = 375
• References = 378
• 14 Serial Input／Output = 379
• 14.1 Serial to Parallel Conversion = 379
• 14.2 A Serial Communications Interface Adapter TBSIA = 388
• 14.3 A Subroutine for Serial I／O through a TBSIA = 393
• 14.4 Interconnecting RS-232 Equipments = 396
• 14.5 Computer Networks = 400
• Problems = 403
• References = 406
• 15 Additional Programming Topics = 407
• 15.1 Pointer Addressing and Stacks = 407
• 15.2 Subroutines = 411
• 15.3 Interrupts = 426
• 15.4 Start-up and Reset = 437
• 15.5 Tables and Other Data Structures = 439
• Problems = 450
• References = 455
• 16 Microprocessor-Based Systems Design = 457
• 16.1 Introduction = 457
• 16.2 Vending Machine Operation = 457
• 16.3 System Specifications = 459
• 16.4 Control Unit Design = 462
• 16.5 Planning the Program = 465
• 16.6 Memory Map Layout = 471
• 16.7 Coding the Program = 475
• Problems = 479
• 17 The Clock-Mode Assumption Reexamined = 481
• 17.1 Attention to Output Waveforms = 481
• 17.2 Elimination of Hazards = 484
• 17.3 Synchronizing Inputs to Clock-Mode Circuits = 486
• 17.4 Clock Skew on Edge-Triggered Flip-Flops = 491
• 17.5 Is That Clock Really Necessary? = 493
• 17.6 Synthesis of Level-Mode Sequential Circuits from a Flow Table = 498
• 17.7 Races in State Variable Transitions = 504
• 17.8 Critical Race-Free State Assignments = 511
• 17.9 More Constraints on Level-Mode Realizations = 516
• Problems = 518
• References = 522
• Appendix A Powers of Two = 523
• Appendix B Summary of TB6502 Instruction Set = 524
• Appendix C TB6502 Instruction Set : Opcodes, Bytes, Cycles = 527
• Appendix D Mapping the TB6502 into the 6502 = 530
• Index = 533