Ultra-dynamic Fine-grained Power and Clock Management Techniques for Microprocessors and Machine Learning Accelerators.

다국어 초록 (Multilingual Abstract)

The increasing prominence of ultra-low power computing applications, such as IoT or wearable devices, require a renewed focus on system-level energy management. Dynamic voltage and frequency scaling (DVFS) has become a widely utilized power management scheme to scale down the microprocessor supply voltage and operation frequency to eliminate the variation protection guardband and save energy consumption. In the commercial SoC chips, each core of the CPU or GPU processors can be powered by independent voltage regulator and clocked by separate clock domain to support flexible power optimization. Although the prior schemes achieve significant energy saving, the operation speed of previous DVFS is still bounded at program level. In another word, the longest exercised critical path delay within the whole program determines the minimum voltage that can be scaled to for each power domain. In fact, there is dynamic timing slack existing within each instruction whenever the longest critical path is not exercised by the runtime instructions. Exploiting the runtime dynamic timing slack can bring promising additional performance/energy gain beyond the conventional DVFS.In this thesis, the ultra-dynamic fine-grained clock and power management scheme operating at instruction level is explored, which lead to significant performance improvement or power saving benefit beyond the conventional program level DVFS management. The instruction-driven adaptive clock management schemes have been explored and developed for (1) a low-power CPU pipeline architecture, (2) a general-purpose GPU architecture, and (3) a PE array based machine learning accelerator architecture. An instruction-driven adaptive clock management through the use of instruction timing encoding and multi-phase all-digital PLL is implemented on a 55nm ARMv7 ISA low power microprocessor. The measurement result shows a 15% performance improvement from proposed clock scheme, which equivalently to up to 28% energy saving benefit. Similar adaptive clocking management scheme is developed on a deep pipelined GPU architecture on a 65nm test chip with hierarchical instruction-driven clocking scheme. The measurement result shows a 18% performance improvement or 30% energy saving from benchmark programs. The dynamic timing slack has also been exploited on the machine learning accelerators by our developed clock chain techniques, which provides multiple clock domains for each PE row and each clock domain loosely synchronized with their neighbors.In addition, a series of fully integrated buck regulator topologies have been developed with novel resonant switching scheme to integrate all the discrete components into silicon, with achieving fast response for the dynamic voltage management. The state-of-the-art power efficiency has been achieved for low power range, with utilizing the fastest switching frequency, i.e. up to 2GHz, reported so far.With the cross-layer design methodology considering from architecture level down to circuit level, the instruction-based dynamic timing slack can be well exploited during runtime. Significant performance improvement or power saving benefits have been obtained on silicon test chips beyond conventional DVFS approaches by our developed ultra-dynamic instruction-driven clock and power management techniques.