디지털 주파수 고정 루프를 가지는 1 ~ 3.2 GHz 서브 샘플링 위상 고정 루프 = 1 ∼ 3.2 GHz Sub-Sampling Phase-Locked Loop with Digital Frequency-Locked Loop

다국어 초록 (Multilingual Abstract)

This paper proposes a Sub-Sampling Phase-Locked Loop (SSPLL) with an output frequency range of 1 to 3.2 GHz for the clock generator of a memory controller. The proposed SSPLL consists of a Sub-Sampling Phase Detector (SSPD), a charge pump, a loop filter, a Voltage-Controlled Oscillator (VCO), and a pulse generator, and a digital frequency-locked loop is added to generate a clock with a wide output frequency range. The proposed SSPLL, using a 20 MHz reference clock, employs a CML buffer to reduce the high gain of the SSPD for a 1 MHz loop bandwidth. It also utilizes a pulse generator capable of controlling pulse width to compensate for changes in the KVCO due to variations in the output clock frequency. The proposed SSPLL is implemented in a 65‑nm CMOS process with a supply voltage of 1.2 V. When generating a 1.8 GHz clock, the SSPLL consumes 8.92 mW of power, and the peak-to-peak and RMS time jitters of the output clock, considering various noise sources, are 7.6 ps and 1.53 ps, respectively.