4Ghz 고성능 CPU 위한 캐시 메모리 시스템

다국어 초록 (Multilingual Abstract)

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy*Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

참고문헌 (Reference)

1 J. Kang, "Way-tracking set-ass ociative caches" 46 : 1497-1499, 2010

2 C. J. Janraj, "Way Sharing Set Associative Cache Archite cture" 251-256, 2012

3 D. Nicolaescu, "Using a Way Cache to Improve Performance of Set-Associative Cache" 4759 : 93-104, 2008

4 S. Santhanam, "StrongARM SA110-a 160MHz 32b 0.5W CMOS ARM processor" 8 : 1996

5 "Samsung DRAM"

6 Henning, John L., "SPEC CPU2006 benchmark descriptions" 34 (34): 1-17, 2006

7 "SPEC Benchmark Suite"

8 Luk, C., "Pin: building customized program analysis tools with dynamic instrumentation" 190-200, 2005

9 "Intel Processor"

10 "Intel Pin-tools"

11 C. H. Ting, "Cycle-Tim e-Aware Sequential Way-Access Set-Associative Cache for Low Energy Consumption" 854-, 2008

12 "CACTI 4.3"

13 Rolan, D, "Adaptive line placement with the Set Balancing Cache" 529-540, 2009

14 J. H. Lee, "A New Cache Architecture Based on Temporal and Spatial Loc ality" 46 : 1451-1467, 2000