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      https://www.riss.kr/link?id=A82499221

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      다국어 초록 (Multilingual Abstract)

      Most existing floorplan techniques use variable models to represent the topology of modules and suggest appropriate algorithms for floorplan on the models. This paper uses a grid model, which is much simpler than any other models, and suggests very effective move operations in the solution space in the simulated annealing frame. The key idea of the suggested effective move operations can be summarized as follows. On the compacted floorplan, it searches floorplan and determines where white (or dead) spaces are. Then, it selects one or two modules around those white spaces and move it to other location in order to change the shape of the white space. Experimental results prove that the suggested technique is comparable with the state-of-the-art techniques.
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      Most existing floorplan techniques use variable models to represent the topology of modules and suggest appropriate algorithms for floorplan on the models. This paper uses a grid model, which is much simpler than any other models, and suggests very ef...

      Most existing floorplan techniques use variable models to represent the topology of modules and suggest appropriate algorithms for floorplan on the models. This paper uses a grid model, which is much simpler than any other models, and suggests very effective move operations in the solution space in the simulated annealing frame. The key idea of the suggested effective move operations can be summarized as follows. On the compacted floorplan, it searches floorplan and determines where white (or dead) spaces are. Then, it selects one or two modules around those white spaces and move it to other location in order to change the shape of the white space. Experimental results prove that the suggested technique is comparable with the state-of-the-art techniques.

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      참고문헌 (Reference)

      1 H. Murata, "VLSI module placement based on rectangular-packing by the sequence-pair" 15 (15): 1518-1524, 1996

      2 E. F. Y. Young, "Twin Binary Sequence: A Nonredundant Representation for General Nonslicing Floorplan" 22 (22): 457-469, 2003

      3 Jai-Ming Lin, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans"

      4 j. -M. Lin, "TCG-S: Orthogonal Coupling of P*-admissible Representati ons for General Floorplans" 842-847, 2002

      5 H. Murata, "Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed Modules" 167-172, 1998

      6 허성우, "O-tree 기반 효과적인 평면계획 알고리즘" 한국정보기술학회 8 (8): 21-27, 2010

      7 S. Nakatake, "Module Placement on BSG-structure and IC Layout Application" 484-490, 1996

      8 T. C. Chen, "Modern Floorplanning Based on Fast Simulated Annealing" 104-112, 2005

      9 Jia Wang, "Linear Constraint Graph for Floorplan Optimization with Soft Blocks" 9-15, 2008

      10 S. Zhou, "ECBL: An Extended Corner Block List with Solution Space including Optimum Placement" 150-155, 2001

      1 H. Murata, "VLSI module placement based on rectangular-packing by the sequence-pair" 15 (15): 1518-1524, 1996

      2 E. F. Y. Young, "Twin Binary Sequence: A Nonredundant Representation for General Nonslicing Floorplan" 22 (22): 457-469, 2003

      3 Jai-Ming Lin, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans"

      4 j. -M. Lin, "TCG-S: Orthogonal Coupling of P*-admissible Representati ons for General Floorplans" 842-847, 2002

      5 H. Murata, "Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed Modules" 167-172, 1998

      6 허성우, "O-tree 기반 효과적인 평면계획 알고리즘" 한국정보기술학회 8 (8): 21-27, 2010

      7 S. Nakatake, "Module Placement on BSG-structure and IC Layout Application" 484-490, 1996

      8 T. C. Chen, "Modern Floorplanning Based on Fast Simulated Annealing" 104-112, 2005

      9 Jia Wang, "Linear Constraint Graph for Floorplan Optimization with Soft Blocks" 9-15, 2008

      10 S. Zhou, "ECBL: An Extended Corner Block List with Solution Space including Optimum Placement" 150-155, 2001

      11 J. Z. Yan, "DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplann er" 161-166, 2008

      12 X. Hong, "Corner Block List: An Effective and Efficient Topological Representation of Non-slicing Floorplan"

      13 Yun-Chih Chang, "B*-Trees: A New Representation for Non Slicing Floorplans" 2001

      14 H. H. Chan, "Are Floorplan Representations Important in Digital Design?" 129-136, 2005

      15 P. -N. Guo, "An O-tree Representation of Non-slicing Floorplan and Its Applications" 268-273, 1999

      16 C. Zhuang, "An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees" 61-68, 2002

      17 Y. Pang, "An Enhanced Perturbing algorithm for Floorplan Design Using the O-tree Representation" 168-173, 2000

      18 H. Zhou, "ACG-Adjacent Constraint Graph for General Floorplans"

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2022 평가예정 재인증평가 신청대상 (재인증)
      2019-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2016-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2012-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2009-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2008-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2006-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.45 0.45 0.39
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.38 0.35 0.566 0.16
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