Analysis and design of energy efficient pipelined SAR ADC using PVT-Robust capacitively degenerated dynamic amplifier|RISS 상세보기

다국어 초록 (Multilingual Abstract)

In this dissertation, analysis and design of energy-efficient pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) using highly linear capacitively degenerated dynamic amplifier as a residue amplifier are discussed, and new practical solutions for this amplifier are proposed.
In the Chapter 2, first, we review the recent design of energy-efficient discrete-time amplifiers that can amplify a residue of pipelined ADCs, and their limitations.
Chapter 3 presents a review of the capacitively degenerated dynamic amplifier, which can achieves power efficiency and high linearity. In addition, we analyze a requirements and limitations as a residue amplifier. The architectural improvements and a practical timing generator for optimal amplification time, which can ensure temperature insensitivity are proposed to achieve high voltage gain and a process, voltage, and temperature (PVT)-robustness. Moreover, detailed noise analysis proves that this amplifier is suitable for stable residue amplification.
Chapter 4 presents a low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) using two-stage capacitively degenerated dynamic amplifier. Improved interstage gain eases the entire pipeline design by alleviating the noise requirement of the following stage. To prove the temperature insensitivity, the measurement against temperatures shows the huge variation of signal-to-noise-and-distortion ratio (SNDR), but performance degradation is fully recovered with adaptive timing generator.
The proposed pipelined SAR ADC suggests the practical solutions of capacitively degenerated dynamic amplifier as a residue amplifier with the recent trend requiring low power consumption.

번역하기

목차 (Table of Contents)

Table of Contents ………………………………………………………………. i
List of Table …………………………………………………………………… iv
List of Figure …………………………………………………………………. iv
Abstract ……………………………………………………………………… viii
1. Introduction ………………………………………………………………… 1

Table of Contents ………………………………………………………………. i
List of Table …………………………………………………………………… iv
List of Figure …………………………………………………………………. iv
Abstract ……………………………………………………………………… viii
1. Introduction ………………………………………………………………… 1
1.1. Motivation and Challenges …………………………………… 1
1.2.A. Pipelined ADC: brief Overview …………………… 3
1.2. Organization of the Dissertation ………………………………… 6
1.3. Copyright ………………………………………………………… 8
2. Review of Energy Efficient Residue Amplifier …………………………… 10
2.1. Introduction ……………………………………………………… 10
2.2. Dynamic Amplifier Topology ……………………………… 13
2.2.A. Ring Amplifier ………………………………………… 13
2.2.B. Floating Inverter Amplifier ………………………… 16
2.2.C. Capacitively-degenerated Dynamic Amplifier …… 18
2.3. Conclusion ……………………………………………………… 22
3. PVT-Robust 2-stage Capacitively-degenerated Dynamic Amplifier …… 23
3.1. Introduction ……………………………………………………… 23
3.2. Limitation of Capacitively-degenerated Dynamic Amplifier … 25
3.2.A. Gain Limitation …………………………………… 25
3.2.B. Parasitic Capacitance Impact ……………………… 31
3.2.C. PVT Immunity ……………………………………… 33
3.3. Proposed Dynamic Amplifier ………………………………… 35
3.2.A. Mismatch Impact …………………………………… 39
3.4. On-chip Timing Generator for Temperature Stabilization … 42
3.5. Noise Calculation and Analysis……………………………… 46
3.5.A. Dynamic Amplifier Core ……………………………. 46
3.5.B. Timing Generator ……………………………………. 47
3.6. Conclusion ……………………………………………………… 53
4. A 50 MS/s 65-dB SNDR Pipelined SAR ADC using Two-Stage Capacitively-Degenerated Dynamic Amplifier ………………………………………… 54
4.1. Introduction ……………………………………………………… 54
4.2. Implementation ………………………………………………… 56
4.3. Residue Transfer ……………………………………………… 62
4.4. Measurements Results …………………………………………… 65
4.5. Conclusion ……………………………………………………… 75
5. Conclusions ……………………………………………………………….… 76
References …………………………………………………………………… 78
국문 요약 …………………………………………………………………... 83
List of Publications …………………………………………………………. 86

참고문헌 (Reference)

1. A SAR-assisted two-stage pipeline ADC, M. P. Flynn, C. C. Lee, vol. 46, no. 4, pp. 859–869, , 2011

2. Ring Amplifiers for Switched Capacitor Circuits, B. Hershberg, K. Sobue, U. -K. Moon, K. Hamashita, S. Weaver, S. Takeuchi, vol. 47, no. 12, pp. 2928-2942, , 2012

3. A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS, B. Verbruggen, J. Craninckx, P. Wambacq, M. Kuijk, G. Van der Plas, vol. 45, no. 10, pp. 2080-2090, , 2010

4. A capacitively degenerated 100-dB linear 20–150 MS/s dynamic amplifier, K. A. A. Makinwa, M. S. Akter, K. Bult, vol. 53, no. 4, pp. 1115–1126, , 2018

5. A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration,, C. R. Grace, S. H. Lewis, P. J. Hurst, vol. 40, no. 5, pp. 1038–1046, , 2005

6. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier, in, X. Tang, vol. 55, no. 4, pp. 1011-1022, , 2020

7. A 1.5 mW 68 dB SNDR 80 Ms/s 2× interleaved pipelined SAR ADC in 28 nm CMOS,, F. Van Der Goes, vol. 49, no. 12, pp. 2835–2845, , 2014

8. A compact 10-b SAR ADC with unit-length capacitors and a passive FIR filter,, P. Harpe, vol. 54, no. 3, pp. 636–645, , 2019

9. A 13-mW 64-dB SNDR 280-MS/s pipelined ADC using linearized integrating amplifiers,, R. Sehgal, K. Bult, F. Van der Goes, vol. 53, no. 7, pp. 1878–1888, , 2018

10. An 11-b 100-MS/s fully dynamic pipelined ADC using a high-linearity dynamic amplifier,, S. Ahn, C. Lim, Y. Park, C. Kim, J. Song, Y. Choi, vol. 55, no. 9, pp. 2468–2477, , 2020