삼차원 집적화를 위한 초박막 실리콘 웨이퍼 연삭 공정이 웨이퍼 표면에 미치는 영향 = Effect of Si Wafer Ultra-thinning on the Silicon Surface for 3D Integration

다국어 초록 (Multilingual Abstract)

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

참고문헌 (Reference)

1 최미경, "웨이퍼 레벨 3D 패키징을 위한 초박막 Si 웨이퍼 공정기술" 대한용접접합학회 26 (26): 12-16, 2008

2 K. Gurnett, "Ultra-thin semiconductor wafer applications and process" 19 (19): 36-40, 2006

3 R.C. Teixeira, "Thickness Characterization of Ultra Thin Wafers on Carrier" 238-241, 2007

4 D. New, "Silicon Thinning and Stacked Packages" 50-52, 2002

5 M. Hendrix, "Advantages of Wet Chemical Spin-Processing for Wafer Thinning and Packaging Applications" 229-236, 2000