1 J. L. Massey, "Shift-register synthesis and BCH decoding" 15 (15): 122-127, 1969
2 B. Park, "Novel folded-KES architecture for high-speed and area-efficient BCH decoders" 64 (64): 535-539, 2017
3 W. Liu, "Low-Power, high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories" 303-308, 2006
4 K. Lee, "Low-Cost, Low-Power and High-Throughput BCH Decoder for NAND Flash Memory" 413-416, 2012
5 김승현, "Investigation of Retention Characteristics Caused by Charge Loss for Charge Trap NAND Flash Memory" 대한전자공학회 17 (17): 584-590, 2017
6 "Forward Error Correction for Submarine Systems. ITU Telecommunication Standardization Sector, ITU-T Recommendation G.975"
7 S. Lin, "Error control coding: Fundamentals and Applications" Prentice-Hall Inc. 2004
8 B. Park, "Area-optimizaed fully-flexible BCH decoder for multiple GF dimensions" 6 : 14498-14509, 2018
9 S. Hwang, "An energy-optimized (37840,34320) symmetric BC-BCH decoder for healthy mobile storages" 169-172, 2017
10 Prashanthi Metku, "Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor" 대한전자공학회 17 (17): 717-728, 2017
1 J. L. Massey, "Shift-register synthesis and BCH decoding" 15 (15): 122-127, 1969
2 B. Park, "Novel folded-KES architecture for high-speed and area-efficient BCH decoders" 64 (64): 535-539, 2017
3 W. Liu, "Low-Power, high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories" 303-308, 2006
4 K. Lee, "Low-Cost, Low-Power and High-Throughput BCH Decoder for NAND Flash Memory" 413-416, 2012
5 김승현, "Investigation of Retention Characteristics Caused by Charge Loss for Charge Trap NAND Flash Memory" 대한전자공학회 17 (17): 584-590, 2017
6 "Forward Error Correction for Submarine Systems. ITU Telecommunication Standardization Sector, ITU-T Recommendation G.975"
7 S. Lin, "Error control coding: Fundamentals and Applications" Prentice-Hall Inc. 2004
8 B. Park, "Area-optimizaed fully-flexible BCH decoder for multiple GF dimensions" 6 : 14498-14509, 2018
9 S. Hwang, "An energy-optimized (37840,34320) symmetric BC-BCH decoder for healthy mobile storages" 169-172, 2017
10 Prashanthi Metku, "Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor" 대한전자공학회 17 (17): 717-728, 2017