A Single-ended Simultaneous Bidirectional Transceiver in 65-nm CMOS Technology|RISS 상세보기

다국어 초록 (Multilingual Abstract)

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than 10<SUP>-12</SUP> with 2<SUP>7</SUP>-1 pseudo-random binary sequence (PRBS) pattern for both signaling directions.

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목차 (Table of Contents)

Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULTANEOUS BIDIRECTIONAL TRANSCEIVER
Ⅲ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSION

Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULTANEOUS BIDIRECTIONAL TRANSCEIVER
Ⅲ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSION
REFERENCES

참고문헌 (Reference)

1 R. J. Drost, "An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS" 39 (39): 1894-1908, 2004

2 B. Casper, "An 8-Gb/s simultaneous bidirectional link with on-die waveform capture" 38 (38): 2111-2120, 2003

3 G. Chandra, "A full-duplex 10Gbase-T transmitter hybrid with SFDR>65dBc over 1 to 400MHz in 40nm CMOS" 144-146, 2011

4 R. Farjad, "A 48-port FCCcompliant 10Gbase-T transmitter with mixed-mode adaptive echo canceller" 47 (47): 3261-3272, 2012

5 J.-H. Kim, "A 4-Gb/s/pin lowpower memory I/O interface using 4-level simultaneous bi-directional signaling" 40 (40): 89-101, 2005

6 J.-K. Kim, "A 3.6Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM" 414-415, 2004

7 Y.-H. Song, "A 0.47-0.66 pJ/bit, 4.8-8Gb/s I/O transceiver in 65nm CMOS" 48 (48): 1276-1289, 2013

8 K. Kaviani, "0.4-mW/Gb/s near-ground receiver front-end with replica transconductance termination calibration for a 16-Gb/s source-series terminated transceiver" 48 (48): 636-648, 2013