Algorithm-Based Error Detection in ATM Cell Schedulers = A Fault-Tolerant ATM Switch

다국어 초록 (Multilingual Abstract)

In this paper, we present an algorithm-based error detection technique for a real-time cell scheduler in ATM switches. The scheduler is designed to realize EDF (earliest deadline first) scheduling to guarantee the end-to-end delay bounds of real-time messages. The algorithm invariants of the scheduler are identified to detect erroneous or out-of-order cell transmissions due to a malfunctioning scheduler. Since a malfunctioning scheduler is unlikely to produce errors detectable at the host level, an immediate detection and recovery at each switch is highly desirable in order to achieve reliable communication in ATM networks. The hardware overhead for realizing error detection is manageably small. Moreover, error detection can be done locally with negligible time overhead.

Shared buffer ATM switches have been attractive since they can achieve a superior performance in terms of cell loss and throughput with a relatively small buffer size. Shared multi-buffer structures have also been considered by several researchers to enhance the access speed of the cell memory for a large switch. High quality services, however, cannot be provided without reliable operation at each module comprising the ATM switches. In this paper, we present a novel on-line error monitoring technique for shared-buffer ATM switches. The technique detects almost all of the functional errors that could occur in the ATM switches. Moreover, it can detect errors with small hardware overhead and negligible time overhead. An early detection of functional errors in ATM switches could not only reduce the wasted bandwidth due to the transmission of erroneous cells, but greatly enhance the recovery time.

목차 (Table of Contents)

• Abstract
• 1. Introduction
• 2. Deadline Assignment for Real-time Cells
• 3. Algorithm Invariants
• 4. Algorithm-Based Error Detection
• 5. Error Detectability
• 6. Conclusions
• References
• On-line Error Monitoring for Shared Buffer ATM Switches
• Abstract
• 1. Introduction
• 2. Functional Error Model
• 3. An error-detectable ATM switch
• 4. Performance Evaluation
• 5. Overhead Estimation
• 6. Conclusion
• References