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      Analysis of High Aspect Ratio Copper Pin Placement Characteristics Using a Particle Dynamics Simulation Model and Process Prediction Based on Experimental Design and Machine Learning

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      https://www.riss.kr/link?id=T17081727

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      다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

      Advanced packaging technologies are continuously facilitating the semiconductor industry in fulfilling the demands for increasingly thinner, smaller, and faster components essential for mobile devices and various high-performance applications. While lead-free solder remains a favored assembly method, tall copper structures, known as copper pillars, are progressively becoming the standard interconnect solution for numerous applications. The prevalent process for forming copper pillars at the wafer level in sophisticated flip chip devices involves lithography and subsequent electroplating. It is essential to devise a pin placement system to supplant the electroplating of copper pins. This research delves into examining the impact of 3D mask design variables on the mounting yield of a novel pin mounting process designed for high-aspect-ratio pins. An analytical approach is deployed to statistically assess the influence of mask hole design parameters on the mounting characteristics. The Taguchi experimental design methodology is utilized to determine analysis conditions and assess their effect on pin mounting yield. The findings reveal that the diameter of the mask hole exerts the most substantial influence on the yield, indicating that larger diameters result in enhanced yields. Furthermore, the signal-to-noise ratio peaks when the pin diameter is at its maximum, implying that a larger hole diameter can achieve high mounting yields irrespective of other factors. Response Surface Methodology (RSM) is then employed to conduct supplementary analyses and statistical evaluations of each design factor. The RSM outcomes validate the predominant impact of mask hole diameter on pin mounting yield, with the analysis of variance (ANOVA) verifying the statistical significance of these results. Experimental validation is carried out under conditions identical to those of the RSM, and although some disparities are observed, the general trends align with the analytical model. These discrepancies are attributed to variations in experimental model scale, fabrication tolerances, and discrepancies in process conditions. Furthermore, a machine learning algorithm is utilized to develop a regression model for different aspect ratios of copper pins with 3D masks. This investigation offers valuable insights for optimizing 3D mask designs to enhance the mounting yield of high-aspect-ratio pins, thereby laying the groundwork for future enhancements in pin mounting processes.

      Keywords: Pin mounting, High-aspect ratio, Optimization, Machine learning, Taguchi
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      Advanced packaging technologies are continuously facilitating the semiconductor industry in fulfilling the demands for increasingly thinner, smaller, and faster components essential for mobile devices and various high-performance applications. While l...

      Advanced packaging technologies are continuously facilitating the semiconductor industry in fulfilling the demands for increasingly thinner, smaller, and faster components essential for mobile devices and various high-performance applications. While lead-free solder remains a favored assembly method, tall copper structures, known as copper pillars, are progressively becoming the standard interconnect solution for numerous applications. The prevalent process for forming copper pillars at the wafer level in sophisticated flip chip devices involves lithography and subsequent electroplating. It is essential to devise a pin placement system to supplant the electroplating of copper pins. This research delves into examining the impact of 3D mask design variables on the mounting yield of a novel pin mounting process designed for high-aspect-ratio pins. An analytical approach is deployed to statistically assess the influence of mask hole design parameters on the mounting characteristics. The Taguchi experimental design methodology is utilized to determine analysis conditions and assess their effect on pin mounting yield. The findings reveal that the diameter of the mask hole exerts the most substantial influence on the yield, indicating that larger diameters result in enhanced yields. Furthermore, the signal-to-noise ratio peaks when the pin diameter is at its maximum, implying that a larger hole diameter can achieve high mounting yields irrespective of other factors. Response Surface Methodology (RSM) is then employed to conduct supplementary analyses and statistical evaluations of each design factor. The RSM outcomes validate the predominant impact of mask hole diameter on pin mounting yield, with the analysis of variance (ANOVA) verifying the statistical significance of these results. Experimental validation is carried out under conditions identical to those of the RSM, and although some disparities are observed, the general trends align with the analytical model. These discrepancies are attributed to variations in experimental model scale, fabrication tolerances, and discrepancies in process conditions. Furthermore, a machine learning algorithm is utilized to develop a regression model for different aspect ratios of copper pins with 3D masks. This investigation offers valuable insights for optimizing 3D mask designs to enhance the mounting yield of high-aspect-ratio pins, thereby laying the groundwork for future enhancements in pin mounting processes.

      Keywords: Pin mounting, High-aspect ratio, Optimization, Machine learning, Taguchi

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      목차 (Table of Contents)

      • Chapter 1 Introduction 1
      • 1.1 Research Background 1
      • 1.1.1 History of semiconductor packaging 2
      • 1.1.2 Technology of semiconductor packaging 2
      • 1.1.3 Advanced semiconductor packaging 6
      • Chapter 1 Introduction 1
      • 1.1 Research Background 1
      • 1.1.1 History of semiconductor packaging 2
      • 1.1.2 Technology of semiconductor packaging 2
      • 1.1.3 Advanced semiconductor packaging 6
      • 1.2 Problem Statement and Research Objective 11
      • 1.3 Literature Review 19
      • 1.3.1 Copper Pillar Fabrication 19
      • 1.3.2 Design of experiment in semiconductor packaging 19
      • 1.3.3 Machine learning in semiconductor packaging 20
      • 1.3.4 CAE in semiconductor packaging 21
      • 1.4 Outline 23
      • Chapter 2 High Aspect-ratio Pin Placement System 24
      • 2.1 Overview 24
      • 2.2 Advantages of Copper Pillar Interconnection 24
      • 2.3 Concept of high aspect-ratio pin mounting mechanism 29
      • 2.4 Stencil Design for High aspect-ratio pin mounting 34
      • 2.5 Laser-assisted Copper Pin Bonding System 40
      • Chapter 3 Computer-aided Analysis of Pin Mounting System 43
      • 3.1 Particle dynamic analysis of pin mounting mechanism 43
      • 3.1.1 Discrete Element Method (DEM) 42
      • 3.1.2 Pin Placement Simulation 44
      • 3.1.3 Simulation Model Validation 53
      • 3.2 Analysis of Pin Bonding Mechanism 59
      • 3.2.1 Structure and Thermal Analysis of Bonding Mechanisms 59
      • 3.2.2 Structure Analysis of Guide Structure 76
      • Chapter 4 Design of Experiment 82
      • 4.1 Design of Experiment in semiconductor packaging process 82
      • 4.2 Parametric analysis of mask hole opening design 82
      • 4.3 Process Optimization using Taguchi Method 96
      • 4.4 Response Surface Methodology 105
      • 4.5 Effect of Design Modification on the Opening Edges 119
      • 4.6 Effect of Processing Parameters on Mounting Yield 129
      • Chapter 5 Yield Prediction using Machine Learning 138
      • 5.1 Overview 138
      • 5.1 Analysis of Collected Dataset Quality 138
      • 5.3 Regression model comparison 149
      • 5.4 Probability-based Mounting Yield and Time Prediction 157
      • Chapter 6 Conclusion 175
      • References 178
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      참고문헌 (Reference)

      1. High-speed Cu electrodeposition and its solderability, Lee, P. T. et al, 320, 559–567, , 2017

      2. High Speed Cu Plating Technology for Wafer Level Packaging, Jia, Z, Wang, J., Wang, D., in 2021 22nd International Conference on Electronic Packaging Technology, ICEPT 2021 (Institute of Electrical and Electronics Engineers Inc. doi:10.1109/ICEPT52650.2021.9568065, , 2021

      3. Improvement of Cu-Pillar Structure Using Advanced Plating Method, Hideo Honma, Jong-Young PARK, oung-Jae KIM, Joo-Hyong NOH, 7, , 2017

      4. High coplanarity and fine pitch copper pillar bumps fabrication method, Chen, C. K., Tsai, T. C., Lee, K. Y., Huang, J. T., Hsu, H. J., 49, , 2010

      5. Optimising pin-in-paste technology using gradient boosted decision trees, Martinek, P., Krammer, O., Soldering and Surface Mount Technology 30, 164–170, , 2018

      6. Optimization of reflow soldering temperature curve based on genetic algorithm, Li, X., Li, M., Jing, S., Yin, P., 7, 772–782, , 2021

      7. Optimization Method for Hot Air Reflow Soldering Process Based on Robust Design, Gong, Y., Ran, L., Chen, D., Chen, C., Processes 11, , 2023

      8. Influence of processing parameters on warpage according to the Taguchi experiment, Guo, W., Zheng, G., Wang, Q., Guo, X, 29, 4153–4158, , 2015

      9. Advanced Lithography and Electroplating Approach to Form High-Aspect Ratio Copper Pillars, Best, K. et al, http://meridian. allenpress. com/ism/article-pdf/2015/1/000793/2257193/isom-2015-thp23. pdf, , 2015

      10. Machine learning based effective linear regression model for TSV layer assignment in 3DIC, Sivakumar, P., Prakash, K. J, Pandiaraj, K., Microprocess Microsyst 83, , 2021

      1. High-speed Cu electrodeposition and its solderability, Lee, P. T. et al, 320, 559–567, , 2017

      2. High Speed Cu Plating Technology for Wafer Level Packaging, Jia, Z, Wang, J., Wang, D., in 2021 22nd International Conference on Electronic Packaging Technology, ICEPT 2021 (Institute of Electrical and Electronics Engineers Inc. doi:10.1109/ICEPT52650.2021.9568065, , 2021

      3. Improvement of Cu-Pillar Structure Using Advanced Plating Method, Hideo Honma, Jong-Young PARK, oung-Jae KIM, Joo-Hyong NOH, 7, , 2017

      4. High coplanarity and fine pitch copper pillar bumps fabrication method, Chen, C. K., Tsai, T. C., Lee, K. Y., Huang, J. T., Hsu, H. J., 49, , 2010

      5. Optimising pin-in-paste technology using gradient boosted decision trees, Martinek, P., Krammer, O., Soldering and Surface Mount Technology 30, 164–170, , 2018

      6. Optimization of reflow soldering temperature curve based on genetic algorithm, Li, X., Li, M., Jing, S., Yin, P., 7, 772–782, , 2021

      7. Optimization Method for Hot Air Reflow Soldering Process Based on Robust Design, Gong, Y., Ran, L., Chen, D., Chen, C., Processes 11, , 2023

      8. Influence of processing parameters on warpage according to the Taguchi experiment, Guo, W., Zheng, G., Wang, Q., Guo, X, 29, 4153–4158, , 2015

      9. Advanced Lithography and Electroplating Approach to Form High-Aspect Ratio Copper Pillars, Best, K. et al, http://meridian. allenpress. com/ism/article-pdf/2015/1/000793/2257193/isom-2015-thp23. pdf, , 2015

      10. Machine learning based effective linear regression model for TSV layer assignment in 3DIC, Sivakumar, P., Prakash, K. J, Pandiaraj, K., Microprocess Microsyst 83, , 2021

      11. Simulation study and parameter optimization of laser TSV using artificial neural networks, Yang, C. H., Lo, Y. L., Karnam, D., 25, 3712–3727 (2023), , 2023

      12. Stress analysis and structural optimization of 3-D IC package based on the Taguchi method, Long, W. M., He, P., Zhang, L., Xiong, M. Y., Soldering and Surface Mount Technology 32, 42–47, , 2020

      13. Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application, Feng, L. et al, Micromachines (Basel) 14, , 2023

      14. Representative volume element analysis for wafer-level warpage using Finite Element methods, Yun, J. C., Park, S. J, Hur, M. J., Baek, J. W., Yang, W. S., 91, 392–398, , 2019

      15. Predictive model of the solder paste stencil printing process by response surface methodology, Chen, C. S., Chen, W. R., Wang, H., Lu, P. J., Kao, Y. C., Soldering and Surface Mount Technology doi:10.1108/SSMT-08-2021-0056, , 2022

      16. Optimal design for vibration reliability of package-on-package assembly using FEA and taguchi method, Cheng, L. X., Xia, J., Li, B., Li, G. Y., IEEE Trans Compon Packaging Manuf Technol 6, 1482–1487, , 2016

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