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      배터리 용량측정을 위한 고해상도 Integrating Sigma-Delta ADC 설계 = Design of a High-Resolution Integrating Sigma-Delta ADC for Battery Capacity Measurement

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      https://www.riss.kr/link?id=A101123962

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      다국어 초록 (Multilingual Abstract)

      Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.
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      Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactl...

      Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

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      참고문헌 (Reference)

      1 J. Robert, "Offset and clock-feedthrough compensated switched-capacitor integrators" 21 : 941-942, 1985

      2 J. Robert, "Offset and clock-feedthrough compensated switched-capacitor integrators" 21 : 941-942, 1985

      3 J. Robert, "Offset and charge injection compensation in an incremental analog-to-digital converter" 45-48, 1985

      4 K. S. Tan, "Error correction techniques for high-performance differential A/D converters" 25 : 1318-1327, 1990

      5 G. Azzopardi, "A Low Voltage High Resolution Pipelined Incremental ADC" 3 : 1499-1502, 1999

      6 T. Ndjountche, "A High-Frequency Double-Sampling Second-Order Delta Sigma Modulator" 52 : 841-845, 2005

      7 J. Robert, "A 16-Bit low-voltage CMOS A/D converter" SC-22 : 157-163, 1987

      8 P. C. Maulik, "A 16-Bit 250-kHz Delta-Sigma Modulator and Decimation Filter" 35 : 458-467, 2000

      1 J. Robert, "Offset and clock-feedthrough compensated switched-capacitor integrators" 21 : 941-942, 1985

      2 J. Robert, "Offset and clock-feedthrough compensated switched-capacitor integrators" 21 : 941-942, 1985

      3 J. Robert, "Offset and charge injection compensation in an incremental analog-to-digital converter" 45-48, 1985

      4 K. S. Tan, "Error correction techniques for high-performance differential A/D converters" 25 : 1318-1327, 1990

      5 G. Azzopardi, "A Low Voltage High Resolution Pipelined Incremental ADC" 3 : 1499-1502, 1999

      6 T. Ndjountche, "A High-Frequency Double-Sampling Second-Order Delta Sigma Modulator" 52 : 841-845, 2005

      7 J. Robert, "A 16-Bit low-voltage CMOS A/D converter" SC-22 : 157-163, 1987

      8 P. C. Maulik, "A 16-Bit 250-kHz Delta-Sigma Modulator and Decimation Filter" 35 : 458-467, 2000

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2024 평가예정 재인증평가 신청대상 (재인증)
      2021-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2020-12-01 평가 등재후보로 하락 (재인증) KCI등재후보
      2017-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2016-01-01 평가 등재후보학술지 유지 (계속평가) KCI등재후보
      2015-12-01 평가 등재후보로 하락 (기타) KCI등재후보
      2011-01-01 평가 등재 1차 FAIL (등재유지) KCI등재
      2009-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2006-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2005-10-17 학술지명변경 외국어명 : 미등록 -> Journal of IKEEE KCI등재후보
      2005-05-30 학술지등록 한글명 : 전기전자학회논문지
      외국어명 : 미등록
      KCI등재후보
      2005-03-25 학회명변경 한글명 : (사) 한국전기전자학회 -> 한국전기전자학회
      영문명 : 미등록 -> Institute of Korean Electrical and Electronics Engineers
      KCI등재후보
      2005-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2004-01-01 평가 등재후보 1차 FAIL (등재후보1차) KCI등재후보
      2003-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.3 0.3 0.29
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.24 0.22 0.262 0.17
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