Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

다국어 초록 (Multilingual Abstract)

In this paper we investigate the effect of a shield metal
line inserted between adjacent bit lines on the refresh time
and noise margin in a planar DRAM cell. The DRAM cell
consists of an access transistor, which is biased to 2.5V
during operation, and an NMOS capacitor having the
capacitance of 10fF per unit cell and a cell size of 3.63 μm2.
We designed a 1Mb DRAM with an open bit-line
structure. It appears that the refresh time is increased
from 4.5 ms to 12 ms when the shield metal line is inserted.
Also, it appears that no failure occurs when Vcc is
increased from 2.2 V to 3 V during a bump up test, while it
fails at 2.8 V without a shield metal line. Raphael
simulation reveals that the coupling noise between
adjacent bit lines is reduced to 1/24 when a shield metal
line is inserted, while total capacitance per bit line is
increased only by 10%.

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