Field-programmable gate array technology

목차 (Table of Contents)

• CONTENTS
• Preface = xi
• Chapter 1. Introduction = 1
• 1.1. Logic Implementation Options = 1
• 1.2. What is an FPGA? = 2
• 1.3. Advantages of FPGAs = 4
• Low Tooling Costs = 4
• Rapid Turnaround = 4
• Low Risk = 5
• Effective Design Verification = 6
• Low Testing Costs = 6
• Standard-Product Advantages = 7
• Life Cycle Advantages = 8
• 1.4. Disadvantages of FPGAs = 8
• Chip Size and Cost = 8
• Speed of Circuitry = 9
• Design Methodology = 9
• 1.5. Technology Trends = 10
• Density = 10
• Speed = 10
• Architecture = 11
• 1.6. Designing for FPGAs = 11
• Design Migration = 11
• 1.7. Outline of subsequent Chapters = 12
• 1. Introduction = 12
• 2. Programming Technology = 13
• 3. Device Architecture = 13
• 4. Software = 13
• 5. The Future = 13
• 6. Design Applications = 13
• 7. Acknowledgments = 13
• 8. References = 13
• 1.8. References = 13
• Chapter 2. SRAM Programmable FPGAs = 15
• 2.1. Introduction = 15
• 2.2. Programming Technology = 15
• SRAM Programming = 15
• Advantages and Disadvantages of SRAM Programming = 17
• 2.3. Device Architecture = 19
• Simple SRAM-Programmable FPGA Architecture = 19
• Design Trade-offs = 23
• The Xilinx XC2000 Architecture = 29
• The Xilinx XC3000 Architecture = 35
• The Xilinx XC4000 Architecture = 43
• Programming the FPGA = 52
• 2.4. Software = 53
• Automated Design Implementation = 54
• Technology-Specific Synthesis = 63
• Manual Design = 63
• 2.5. The Future = 65
• Programming Technology = 65
• Architecture = 66
• Software = 66
• Partitioning in Space and Time = 67
• Design Methodology = 67
• 2.6. Design Applications = 68
• General Design Issues = 68
• Counter Examples = 70
• Efficient Multiplication by a Constant in an Artificial Neural Network = 75
• Distributed Arithmetic for Signal Processing = 77
• Applications of Reprogramming = 79
• A Fast Video Controller = 83
• A Position Tracker For a Robot Manipulator = 84
• A Fast DMA Controller = 85
• Custom Computing Applications = 87
• 2.7. Acknowledgments = 90
• 2.8 References = 91
• Chapter 3. Antifuse Programmed FPGAs = 97
• 3.1. Introduction = 97
• 3.2. Programming Technology = 99
• 3.3. Device Architecture = 103
• Principles of Programmable Routing = 103
• Routing Architecture of the Actel FPGAs = 108
• Act1 Architecture = 110
• Act2 Architecture = 113
• Act3 Architecture = 117
• Programming and Testing = 118
• Capacity = 124
• Performance = 127
• 3.4. Software = 128
• 3.5. The Future = 132
• 3.6. Design Applications = 133
• Designing with ACT1 and ACT2 FPGAs = 133
• Designing with ACT FPGAs : A TTL Perspective = 137
• Migrating PLD Designs to FPGAs = 140
• Synthesis Design Flow = 143
• Designing Counters with ACT Devices = 144
• Designing Adders and Accumulators with the ACT Architecture = 153
• State Machine Design = 160
• Using FPGAs for Digital PLLs = 164
• Customer Design Examples = 167
• 3.7. Acknowledgments = 168
• 3.8. References = 168
• Chapter 4. Erasable Programmable Logic Devices = 171
• 4.1. Introduction = 171
• 4.2. Programming Technology = 173
• Logic Structures Using EPROM Transistors = 175
• 4.3. Device Architecture = 179
• Basic Concepts = 179
• Macrocell Architecture = 180
• Logic Array = 180
• Programmable Flip-Flops = 181
• Programmable Clock = 182
• I／O Control Block = 182
• Design Security = 182
• Functional Testing = 183
• Operating Requirements for EPLDs = 183
• Architectural Evolution in Array-Based PLDs = 184
• 4.3.1. The "Classic" Family of PLDs = 184
• Functional Description of the EP1810 = 184
• 4.3.2. The MAX(Multiple Array matriX) Product Family = 187
• 4.3.3. MAX 7000 = 195
• 4.3.4. MPLDs : Mask-Programmed Logic Devices = 200
• 4.4. Software = 204
• 4.5. The Future = 218
• 4.6. Design Applications = 224
• 4.6.1. MAX 5000 Timing = 224
• 4.6.2. Using Expanders to Build Registered Logic in MAX EPLDs = 228
• 4.6.3. Simulating Internal Buses in General-Purpose EPLDs = 233
• 4.6.4. Fast Bus Controllers with the EPM5016 = 238
• 4.6.5. Micro Channel Bus Master and SDP Logic with the EPM5032 EPLD = 240
• 4.6.6. FIFO Controller Using an EPM7096 = 243
• 4.6.7. Integrating an Intelligent I／O Subsystem with a Single EPM5130 EPLD = 246
• 4.6.8. Controlling Complex CCD Imaging Systems with the EPS464 EPLD = 247
• 4.7. References = 250
• Index = 253