멀티 코어 프로세서를 위한 저전력 필터 캐쉬 설계 기법

다국어 초록 (Multilingual Abstract)

Energy consumption as well as performance should be considered when designing up-to-date multicore processors. In this paper, we propose new design technique to reduce the energy consumption in the instruction cache for multicore processors by using modified filter cache. The filter cache has been recognized as one of the most energy-efficient design techniques for singlecore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential to reduce the energy consumption in a multicore processor. The proposed technique reduces the energy consumption in the instruction cache for multicore processors by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed architecture reduces the energy consumption in the instruction cache for multicore processors by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.

참고문헌 (Reference)

1 양나라, "임베디드 시스템에서 후방 분기 명령어 정보를 이용한 저전력 명령어 캐쉬 설계 기법" 한국컴퓨터정보학회 13 (13): 33-40, 2008

2 공준호, "인텔 펜티엄 4와 코어2 듀오의 실행시간과 파워소모량 효율성 비교" 한국컴퓨터정보학회 13 (13): 165-172, 2008

3 곽종욱, "모드 선택 비트를 사용한 필터 캐시 예측기" 대한전자공학회 46 (46): 1-13, 2009

4 이광용, "멀티코어 기술 및 산업 동향" (1295) : 2007

5 K. Inonue, "Way-predicting Set-associative Cache for High Performance and Low Energy Consumption" Proceedings of the International Symposium on Low Power Electronics and Design 273-275, 1999

6 J. Kin, "The Filter Cache: An Energy Efficient Memory Structure" 184-193, 1997

7 D. H. Albonesi, "Selective Cache Ways: On-demand Cache Resource Allocation" 70-75, 1999

8 "SPEC CPU 2000 Benchmarks"

9 M. Powell, "Reducing Set-associative Cache Energy via Way-prediction and Selective Direct-mapping" 54-65, 2001

10 C. H. Kim, "PP-cache: A Partitioned Power-aware Instruction Cache Architecture" 30 : 268-279, 2006

11 S. Segars, "Low Power Design Techniques for Microprocessors" 2001

12 N. P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers" 364-373, 1990

13 D. Burger, "Evaluating Future Micro-Processors: the SimpleScalar tool set" Univ. of Wisconsin-Madison Computer Sciences Dept. 1997

14 P. Shivakumar, "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model" 2001