TCAD-Based Variability Analysis and Optimization in 28-nm Ternary-CMOS Technology

다국어 초록 (Multilingual Abstract)

To overcome the limitations in power efficiency and information density of complementary metal- oxide-semiconductor (CMOS) technology, shifting from a binary to a ternary logic system has been proposed as a promising solution. Recently, we demonstrated a power-scalable and mass-producible Ternary-CMOS (T-CMOS) technology using a commercial 28nm foundry. This technology employs a highly doped retrograde channel doping profile to leverage band-to-band tunneling (BTBT) mechanism at the body-to-drain junction, enabling a constant off-state BTBT current (IBTBT). This mechanism creates a third voltage state, which is essential for obtaining ternary operation. A key advantage of the tunneling-based ternary device platform is its ability to scale both static and dynamic power consumption by scaling IOFF and supply voltage (VDD) due to the exponential dependence of tunneling current on VDS. Moreover, this platform can be implemented through simple doping process tuning, supporting CMOS-compatible designs and allowing commercialization within ultra-large-scale integrated circuits at the level of conventional CMOS.
Despite these advantages, T-CMOS faces several critical challenges for successful commercialization. A key challenge is ensuring robust operation. The division into three states (0, 1, and 2) inherently lowers the noise margin compared to binary logic. This makes it more difficult to achieve reliable functionality. T-CMOS is well-suited for low-power operation due to its scalable VDD. However, these VDD scaling aggravates noise margin issues in ternary logic. The ternary system becomes increasingly vulnerable to process variations. This variability issues significantly weaken the stability of ternary inverters, leading to reliability problems with stored data. Previous studies have demonstrated that the output mid-state voltage variation (ΔVOM) is logarithmically reduced despite significant ΔIBTBT. However, the transition voltage variation (ΔVTR), which reduces the noise margin of all states (0, 1, and 2) in ternary logic, remains unresolved. This issue can be addressed by reducing threshold voltage (VT) variation. Overcoming these challenges requires innovative design solutions and advanced variability control techniques.
This paper proposes an advanced T-CMOS technology development framework to mitigate variability. This approach utilizes TCAD simulations to calibrate extensive measurement data and analyze the electrical and variability characteristics of ternary devices. Additionally, it optimizes variability through process engineering based on the analysis results. C-V calibration was performed to analyze interface trap density (Dit) and channel doping concentration (Nch), while I-V calibration was used to evaluate off-state leakage (IOFF), subthreshold swing (SSW), Threshold voltage (VT) roll-off, and drain- induced barrier lowering (DIBL). These analyses enabled the characterization of scalable T-CMOS devices immune to short-channel effects under various ion implantation (I/I) conditions. Subsequently, statistical impedance field method (sIFM) tool is utilized to analyze key variability sources, including Random Dopant Fluctuation (RDF), Interface Trap Fluctuation (ITF), and Line Edge Roughness (LER).
Based on the comprehensive characterization and analysis, we propose a novel design methodology called Gate-Underlap T-CMOS to optimize variability in the ternary device platform. The key idea is to reduce RDF, the dominant variability source, by extending the effective channel length through LDD engineering. This technique can also be applied to CMOS to mitigate variability and short-channel effects (SCE), but it involves a trade-off of ION degradation. However, since our ternary device operates in the off-state, it takes full advantage of this approach without performance degradation caused by ION reduction.
By applying this approach, the effective channel length (Leff) increased by 1.26x/1.33x, and VT variability decreased by 0.84x/0.81x. Consequently, the reduction in ΔVTR, which significantly impacts the noise margin (NM) of the ternary inverter, resulted in a 29% improvement in NM, increasing it from 82 mV to 106 mV. These advancements address key challenges for the commercialization of T-CMOS, providing a platform for energy-efficient and mass-producible ternary devices.

목차 (Table of Contents)

• I. Introduction
• 1.1 The Power Scaling Limits of CMOS
• 1.1.1 Needs of New Device Technology
• 1.1.2 Ternary System
• 1.2 Wafer-Scale Integrated T-CMOS in 110-/90-/28-nm Foundries
• 1.2.1 Operation Principle: Tunneling-Based T-CMOS in the Off-State Operation
• 1.2.2 Highly-Scalable T-CMOS Technology
• 1.3 Variability Issue in T-CMOS
• 1.4 Motivation: Design of Process Variation-Tolerant T-CMOS
• II. TCAD Calibration of Highly-Scalable and Short-Channel Effect Immune 28-nm Ternary Device
• 2.1 1-D C-V Calibration
• 2.1.1 EOT and Npoly Analysis: Independent of I/I condition
• 2.1.2 Nch and Dit Analysis: Dependent on I/I condition
• 2.2 2-D I-V Calibration
• 2.2.1 Tunneling leakage and SSW Analysis: Less Affected by Gate Length
• 2.2.2 VT roll-off and DIBL Analysis: Dependent on Gate Length
• III. Process Variation in T-CMOS
• 3.1 Variability Analysis Framework
• 3.1.1 Sources of random variations
• 3.1.2 Statistical Impedance Field Method
• 3.2 Process Variation Behavior due to Highly-Doped p-n Junctions
• 3.2.1 VT and IOFF Variability Results
• 3.2.2 VT Variability Analysis under Increasing Channel Doping Concentration
• 3.2.3 IOFF Variability Analysis under Increasing Effective Doping Concentration
• IV. Proposed Variation-Tolerant T-CMOS with LDD Engineering
• 4.1 Design Methodology of Gate-Underlap T-CMOS
• 4.1.1 Strategy to Minimize VT Variability
• 4.1.2 Ternary Device Characteristics with Extended Underlap Length
• 4.2 Device Optimization for Robust T-CMOS Stability
• 4.2.1 Improved Device Variability Through Increased Effective Channel Length
• 4.2.2 Enhanced Noise Margin for Stable Ternary Operation
• V. Further Work
• 5.1 Gate underlap T-CMOS with halo implantation
• 5.2 Variability-Aware Design Technology Co-Optimization (DTCO)
• VI. Conclusion
• Reference