Synchronous Mirror Delay for Zero-and Multi-Phase Locking

다국어 초록 (Multilingual Abstract)

A clock generation circuit used in synchronous SRAM (static random access memory) was designed
by adapting SMD (synchronous mirror delay) scheme. A multi-phase synchronous circuit
suited for the double data rate specication was designed using this clock generation circuit. The
unit delay stage composed of a self-resetting scheme was used for the purposes of high-stability
SMD operation and reduction of the synchronizing error. The synchronizing error of SMD was
reduced under the delay time of the unit delay stage by the compensation characteristics of the
detecting circuit. The simulation, which is performed by using HSPICE with the SEC1 0.13 m
model parameter, showed that the delay time of unit delay stage was about 50 ps under the standard
conditions (1.2 V, 80 C). Because of the compensating eect of the detecting circuits, the
synchronizing error of SMD could be reduced to 15 ps, which is smaller than the delay time of
the unit delay stage. For the zero-phase clock generation circuit including SMD, the clock receiver,
the clock driver, and other additional circuits, the synchronizing error was less than 20 ps. The
simulated maximum current, considering the load of the data receiver, the address receiver, the
control receiver and the metal line, was 59 mA. Compared with the timing characteristics of a 500
MHz SRAM, these results show that the synchronizing error is 1/20 of the timing margin under
a DDR input and that the current consumption is 1/40 of the total current consumption of the
SRAM.