H.264 비디오 코덱을 위한 효율적인 움직임 추정 알고리즘과 회로 구조 = Efficient Motion Estimation Algorithm and Circuit Architecture for H.264 Video CODEC

국문 초록 (Abstract)

본 논문은 H.264 비디오 코덱에 적용할 수 있는 고성능 정수화소 움직임 예측 회로 구조에 대해 설명한다. 전역 탐색 알고리즘은 모든 가능한 블록에 대해 확인하기 때문에 가장 좋은 결과를 보장한다. 그러나 전역 탐색 알고리즘은 많은 양의 연산과 데이터를 요구한다. 연산 노력을 줄이기 위해 많은 고속 탐색 알고리즘들이 제안되었다. 고속 탐색 알고리즘들의 단점은 데이터 접근이 불규칙하고 데이터 재사용이 어려운 것이다. 본 논문에서는 고성능 움직임 예측을 위하여 효율적인 정수화소 움직임 예측 알고리즘을 제안하고 있으며, 이를 구현하기 위한 처리 속도가 높고 외부 메모리 사용을 줄일 수 있는 회로 구조를 제안한다. 제안한 회로는 7가지 종류의 가변 블록 크기를 지원하면 41개 움직임 벡터를 생성한다. 구현된 고성능 움직임 예측회로는 RTL로 구현하였고 FPGA가 탑재된 보드에서 동작을 검증하였다. 130㎚ CMOS 표준 셀 라이브러리로 합성된 회로는 1초에 139.8장의 1080HD (1,920x1,088) 영상을 처리할 수 있고 H.264 5.1 레벨까지 지원 가능하다.

다국어 초록 (Multilingual Abstract)

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at RTL and verified its operation on FPGA board. The circuit synthesized by using 130㎚ CMOS standard cell library processes 139.8 1080HD (1,920x1,088) image frames per second and supports up to H.264 level 5.1.

목차 (Table of Contents)

• 요약
• Abstract
• Ⅰ. Introduction
• Ⅱ. Proposed Integer-pel ME Algorithm
• Ⅲ. Proposed Circuit Architecture
• Ⅳ. Implementation Results
• Ⅳ. 결론
• References
• 저자소개

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