Investigation of the Channel-Width Dependence of CHEI Program/HHI Erase Cycling Behavior in Nitride-Based Charge-Trapping Flash (CTF) Memory Devices

다국어 초록 (Multilingual Abstract)

The channel-width dependence of program/erase cycling behavior in
nitride-based charge-trap flash memory devices is investigated. When
the program/erase is conducted by a channel-hot-electron-injection
(CHEI) program/hot-hole-injection (HHI) erase, respectively, while a
trapped-charge-profile-dependent overerasure is observed clearly in
a wide device, it is suppressed in a narrow device. The
channel-width dependence is featured in both the overerasure
suppression and the gradual positive shift of the threshold voltage
in narrow devices. This is explained as an elevated
hot-hole-injection erase efficiency in the channel-center region and
a suppression of the lateral migration of injected holes in the
channel-edge region by combining the measured endurance
characteristics and Technology Computer-Aided Designs (TCAD) device
simulation results. The main physical mechanisms are the
three-dimensional distribution of the electric field by gate/drain
voltage, increasing interface states, and their trapped charge
during program/erase cycling in the channel-edge region.

다국어 초록 (Multilingual Abstract)

The channel-width dependence of program/erase cycling behavior in
nitride-based charge-trap flash memory devices is investigated. When
the program/erase is conducted by a channel-hot-electron-injection
(CHEI) program/hot-hole-injection (HHI) erase, respectively, while a
trapped-charge-profile-dependent overerasure is observed clearly in
a wide device, it is suppressed in a narrow device. The
channel-width dependence is featured in both the overerasure
suppression and the gradual positive shift of the threshold voltage
in narrow devices. This is explained as an elevated
hot-hole-injection erase efficiency in the channel-center region and
a suppression of the lateral migration of injected holes in the
channel-edge region by combining the measured endurance
characteristics and Technology Computer-Aided Designs (TCAD) device
simulation results. The main physical mechanisms are the
three-dimensional distribution of the electric field by gate/drain
voltage, increasing interface states, and their trapped charge
during program/erase cycling in the channel-edge region.

참고문헌 (Reference)

1 A. Furnemont, 66-, 2006

2 A. Furnemont, 28 : 276-, 2007

3 A. Furnemont, 54 : 1351-, 2007

4 M. Nishigohri, 881-, 1996

5 J.-D. Lee, 4 : 110-, 2004

6 A. Shappir, 47 : 937-, 2003

7 E. Lusky, 22 : 556-, 2001

8 M. H. White, 16 : 22-, 2000

9 B. Eitan, 21 : 543-, 2000

10 H.-T. Lue, 53 : 119-, 2006

11 C.-C. Yeh, 25 : 643-, 2004

12 S.-H. Gu, 53 : 103-, 2006

13 W.-J. Tsai, 34-, 2002

14 W.-J. Tsai, 522-, 2004

15 W.-J. Tsai, 53 : 808-, 2006

16 A. Shappir, 72 : 426-, 2004

17 IlHwanCho, "Nano-Scale SONOS Memory with a Double-Gate MOSFET Structure" 한국물리학회 42 (42): 233-236, 2003

18 Il Hwan Cho, "Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device Built on a Bulk Si Wafer" 한국물리학회 44 (44): 83-86, 2004