온칩 테스트 로직을 이용한 TSV 결함 검출 방법

다국어 초록 (Multilingual Abstract)

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

목차 (Table of Contents)

• Abstract
• 1. 서론
• 2. 기존 TSV 테스트 기법
• 3. TSV 미세결함 검출을 위한 온칩 테스터
• 4. 제안 회로의 효율성 및 활용방안
• References

참고문헌 (Reference)

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