계층적 블럭매칭 알고리즘을 위한 파이프라인식 VLSI 아키텍쳐 = Pipelined VLSI Architectures for the Hierarchical Block-Matching Algorithm

다국어 초록 (Multilingual Abstract)

This paper presents two parallel VLSI architectures for the hierarchical block-matching algorithm (HBMA). The repeated procedure of HBMA and the billnear interpolation cause the data dependences that are obstacles in parallel processing. The proposed architectures have the pipeline scheme to mainly solve the interlayer data dependency. From two possible order of vector flow, two specific three-stage architectures are designed based on the given parameters of HBMA. U-Architecture follows the unidirectional scan order and B-Architecture follows the bidirectional scan order. The internal memory and the interpolation unit can fulfill the designated scan order in synchronous way. The performance results show that both architectures can process in real-time up to the broadcast video format under the current VLSI technology, and the HDTV video format with the near future VLSI capabilities. Both architectures also achieve nearly linear speedup over an assumed non-pipelined VLSI architecture. Compared to U-Architecture, B-Architecture reduces 50% of pin count owing to the wraparound memory scheme.