영상처리용 DCT 구조의 RT 레벨 설계 = RT Level Architecture Design of Image Processing DCT

다국어 초록 (Multilingual Abstract)

This paper represents a Register Transfer(RT) level architecture design for a DCT chip. The architecture exploits highly parallel and pipelined scheme to apply it to high speed image applications. Using a distributed arithmetic instead of a multiplication, the chip area can be reduced dramatically. Two separate NxN 1D-DCT/IDCT, a transpose RAM, and two controllers are the basic structure. With variations to bit width of input/output, the modulized 1D-IDCT structure can be adopted easily to 2D-IDCT, 1D-DCT, and 2D-DCT. The proposed architecture for IDCT is modeled with VHDL and synthesized to gate level. The simulation result by VHDL shows that the designed architecture can handle in image compression/decompression with 100MHz clock frequency.